Searched refs:XE_REG_OPTION_MASKED (Results 1 – 6 of 6) sorted by relevance
| /drivers/gpu/drm/xe/regs/ |
| A D | xe_gt_regs.h | 102 #define WM_CHICKEN3 XE_REG_MCR(0x5588, XE_REG_OPTION_MASKED)
118 #define VFLSKPD XE_REG_MCR(0x62a8, XE_REG_OPTION_MASKED)
133 #define CACHE_MODE_1 XE_REG(0x7004, XE_REG_OPTION_MASKED)
139 #define HIZ_CHICKEN XE_REG(0x7018, XE_REG_OPTION_MASKED)
143 #define XEHP_PSS_MODE2 XE_REG_MCR(0x703c, XE_REG_OPTION_MASKED)
174 #define VF_PREEMPTION XE_REG(0x83a4, XE_REG_OPTION_MASKED)
177 #define VF_SCRATCHPAD XE_REG(0x83a8, XE_REG_OPTION_MASKED)
499 #define ROW_CHICKEN XE_REG_MCR(0xe4f0, XE_REG_OPTION_MASKED)
523 #define TDL_CHICKEN XE_REG_MCR(0xe5f4, XE_REG_OPTION_MASKED)
546 #define RCU_MODE XE_REG(0x14800, XE_REG_OPTION_MASKED)
[all …]
|
| A D | xe_engine_regs.h | 63 #define RING_PSMI_CTL(base) XE_REG((base) + 0x50, XE_REG_OPTION_MASKED)
95 #define INSTPM(base) XE_REG((base) + 0xc0, XE_REG_OPTION_MASKED)
98 #define RING_CMD_CCTL(base) XE_REG((base) + 0xc4, XE_REG_OPTION_MASKED)
109 #define CSFE_CHICKEN1(base) XE_REG((base) + 0xd4, XE_REG_OPTION_MASKED)
114 #define FF_SLICE_CS_CHICKEN1(base) XE_REG((base) + 0xe0, XE_REG_OPTION_MASKED)
117 #define CS_DEBUG_MODE1(base) XE_REG((base) + 0xec, XE_REG_OPTION_MASKED)
126 #define BCS_SWCTRL(base) XE_REG((base) + 0x200, XE_REG_OPTION_MASKED)
141 #define RING_CONTEXT_CONTROL(base) XE_REG((base) + 0x244, XE_REG_OPTION_MASKED)
188 #define CS_CHICKEN1(base) XE_REG((base) + 0x580, XE_REG_OPTION_MASKED)
|
| A D | xe_eu_stall_regs.h | 18 #define XEHPC_EUSTALL_REPORT XE_REG_MCR(0xe528, XE_REG_OPTION_MASKED)
22 #define XEHPC_EUSTALL_REPORT1 XE_REG_MCR(0xe52c, XE_REG_OPTION_MASKED)
25 #define XEHPC_EUSTALL_CTRL XE_REG_MCR(0xe53c, XE_REG_OPTION_MASKED)
|
| A D | xe_reg_defs.h | 91 #define XE_REG_OPTION_MASKED .masked = 1 macro
|
| A D | xe_oa_regs.h | 59 #define OAG_OA_DEBUG XE_REG(0xdaf8, XE_REG_OPTION_MASKED)
|
| /drivers/gpu/drm/xe/tests/ |
| A D | xe_rtp_test.c | 29 #define MASKED_REG1 XE_REG(1, XE_REG_OPTION_MASKED)
|
Completed in 18 milliseconds