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Searched refs:ZL_REF_MB_SEM_RD (Results 1 – 3 of 3) sorted by relevance

/drivers/dpll/zl3073x/
A Ddpll.c122 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD, in zl3073x_dpll_input_ref_frequency_get()
179 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD, in zl3073x_dpll_input_pin_esync_get()
238 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD, in zl3073x_dpll_input_pin_esync_set()
332 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD, in zl3073x_dpll_input_pin_frequency_set()
610 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD, in zl3073x_dpll_input_pin_phase_adjust_get()
655 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD, in zl3073x_dpll_input_pin_phase_adjust_set()
A Dregs.h179 #define ZL_REF_MB_SEM_RD BIT(1) macro
A Dcore.c480 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD, in zl3073x_ref_state_fetch()

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