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Searched refs:ZL_REG_REF_ESYNC_DIV (Results 1 – 2 of 2) sorted by relevance

/drivers/dpll/zl3073x/
A Dregs.h197 #define ZL_REG_REF_ESYNC_DIV ZL_REG(10, 0x30, 4) macro
A Ddpll.c190 rc = zl3073x_read_u32(zldev, ZL_REG_REF_ESYNC_DIV, &esync_div); in zl3073x_dpll_input_pin_esync_get()
264 rc = zl3073x_write_u32(zldev, ZL_REG_REF_ESYNC_DIV, in zl3073x_dpll_input_pin_esync_set()

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