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Searched refs:_3 (Results 1 – 11 of 11) sorted by relevance

/drivers/hid/bpf/progs/
A Dhid_bpf_helpers.h159 _1, _2, _3, _4, _5, _6, _7, _8, \ argument
169 #define _ARG3(_1, _2, _3) _1; _2; _3; argument
170 #define _ARG4(_1, _2, _3, _4) _1; _2; _3; _4; argument
171 #define _ARG5(_1, _2, _3, _4, _5) _1; _2; _3; _4; _5; argument
172 #define _ARG6(_1, _2, _3, _4, _5, _6) _1; _2; _3; _4; _5; _6; argument
173 #define _ARG7(_1, _2, _3, _4, _5, _6, _7) _1; _2; _3; _4; _5; _6; _… argument
174 #define _ARG8(_1, _2, _3, _4, _5, _6, _7, _8) _1; _2; _3; _4; _5; _6; _… argument
175 #define _ARG9(_1, _2, _3, _4, _5, _6, _7, _8, _9) _1; _2; _3; _4; _5; _6; _… argument
176 #define _ARG10(_1, _2, _3, _4, _5, _6, _7, _8, _9, _a) _1; _2; _3; _4; _5; _6; … argument
177 #define _ARG11(_1, _2, _3, _4, _5, _6, _7, _8, _9, _a, _b) _1; _2; _3; _4; _5; _6; … argument
[all …]
/drivers/gpu/drm/nouveau/include/nvhw/
A Ddrf.h65 #define NVVAL_(X,_1,_2,_3,_4,_5,IMPL,...) IMPL argument
70 #define NVDEF_(X,_1,_2,_3,_4,_5,IMPL,...) IMPL argument
76 #define NVVAL_GET_(X,_1,_2,_3,_4,_5,IMPL,...) IMPL argument
93 #define NVVAL_SET_(X,_1,_2,_3,_4,_5,_6,IMPL,...) IMPL argument
98 #define NVDEF_SET_(X,_1,_2,_3,_4,_5,_6,IMPL,...) IMPL argument
107 #define NVVAL_MW_GET_(X,_1,_2,_3,_4,_5,IMPL,...) IMPL argument
117 #define NVVAL_MW_SET_(X,_1,_2,_3,_4,_5,_6,IMPL,...) IMPL argument
122 #define NVDEF_MW_SET_(X,_1,_2,_3,_4,_5,_6,IMPL,...) IMPL argument
129 #define DRF_RD_(X,_1,_2,_3,_4,_5,_6,IMPL,...) IMPL argument
136 #define DRF_WR_(X,_1,_2,_3,_4,_5,_6,_7,IMPL,...) IMPL argument
[all …]
/drivers/gpu/drm/nouveau/dispnv50/
A Dovly827e.c73 if (NVBO_TD32(bo, offset, NV_DISP_NOTIFICATION_1, _3, STATUS, ==, BEGUN)) in ovly827e_ntfy_wait_begun()
86 NVBO_WR32(bo, offset, NV_DISP_NOTIFICATION_1, _3, in ovly827e_ntfy_reset()
87 NVDEF(NV_DISP_NOTIFICATION_1, _3, STATUS, NOT_BEGUN)); in ovly827e_ntfy_reset()
A Dcorec37d.c100 NVBO_WR32(bo, offset, NV_DISP_NOTIFIER, _3, 0); in corec37d_ntfy_init()
/drivers/firmware/psci/
A Dpsci.c350 invoke_psci_fn(PSCI_FN_NATIVE(1_3, SYSTEM_OFF2), 0, 0, 0); in psci_sys_hibernate()
398 PSCI_ID_NATIVE(1_3, SYSTEM_OFF2),
564 ret = psci_features(PSCI_FN_NATIVE(1_3, SYSTEM_OFF2)); in psci_init_system_off2()
/drivers/net/ethernet/marvell/octeontx2/af/
A Dmbox.c550 #define M(_name, _id, _1, _2, _3) case _id: return # _name; in otx2_mbox_id2name() argument
554 #define M(_name, _id, _1, _2, _3) case _id: return # _name; in otx2_mbox_id2name() argument
558 #define M(_name, _id, _1, _2, _3) case _id: return # _name; in otx2_mbox_id2name() argument
A Dmbox.h404 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, argument
/drivers/net/ethernet/mellanox/mlx5/core/
A Den_stats.c855 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(802_3)
860 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(802_3)
868 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(802_3)
882 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(802_3)
2575 MLX5E_DEFINE_STATS_GRP(802_3, MLX5E_NDO_UPDATE_STATS);
2595 &MLX5E_STATS_GRP(802_3),
A Den_stats.h524 extern MLX5E_DECLARE_STATS_GRP(802_3);
A Den_rep.c1402 &MLX5E_STATS_GRP(802_3),
/drivers/net/ethernet/mellanox/mlx5/core/ipoib/
A Dipoib.c471 &MLX5E_STATS_GRP(802_3),

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