Searched refs:_MASKED_FIELD (Results 1 – 5 of 5) sorted by relevance
| /drivers/gpu/drm/i915/ |
| A D | i915_reg_defs.h | 109 #define _MASKED_FIELD(mask, value) ({ \ macro
118 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
119 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
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| A D | i915_perf.c | 2637 _MASKED_FIELD(GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE, in gen12_configure_oar_context()
2849 return _MASKED_FIELD(GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS, in oag_report_ctx_switches()
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| /drivers/gpu/drm/xe/ |
| A D | xe_eu_stall.c | 482 read_ptr_reg = _MASKED_FIELD(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, read_ptr_reg); in xe_eu_stall_data_buf_read()
663 read_ptr_reg = _MASKED_FIELD(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, read_ptr_reg); in xe_eu_stall_stream_enable()
675 reg_value = _MASKED_FIELD(EUSTALL_MOCS | EUSTALL_SAMPLE_RATE, in xe_eu_stall_stream_enable()
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| A D | xe_oa.c | 760 _MASKED_FIELD(CTX_CTRL_OAC_CONTEXT_ENABLE, in xe_oa_configure_oar_context()
784 _MASKED_FIELD(CTX_CTRL_OAC_CONTEXT_ENABLE, in xe_oa_configure_oac_context()
786 _MASKED_FIELD(CTX_CTRL_RUN_ALONE, enable ? CTX_CTRL_RUN_ALONE : 0), in xe_oa_configure_oac_context()
814 return _MASKED_FIELD(OAG_OA_DEBUG_DISABLE_MMIO_TRG, in oag_configure_mmio_trigger()
1060 return _MASKED_FIELD(OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS, in oag_report_ctx_switches()
1067 return _MASKED_FIELD(OAG_OA_DEBUG_BUF_SIZE_SELECT, in oag_buf_size_select()
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| /drivers/gpu/drm/i915/gt/ |
| A D | intel_workarounds.c | 326 wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); in wa_masked_field_set()
333 wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); in wa_mcr_masked_field_set()
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