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Searched refs:_PICK (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/i915/display/
A Dintel_hdcp_regs.h74 #define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \
187 #define _PORT_HDCP2_BASE(port, x) _MMIO(_PICK((port), \
238 #define PIPE_HDCP2_STREAM_STATUS(pipe) _MMIO(_PICK((pipe), \
A Dintel_cx0_phy_regs.h125 #define XELPDP_LANE_PIPE_RESET(lane) _PICK(lane, REG_BIT(31), REG_BIT(30))
126 #define XELPDP_LANE_PHY_CURRENT_STATUS(lane) _PICK(lane, REG_BIT(29), REG_BIT(28))
127 #define XELPDP_LANE_POWERDOWN_UPDATE(lane) _PICK(lane, REG_BIT(25), REG_BIT(24))
132 #define XELPDP_LANE_POWERDOWN_NEW_STATE(lane, val) _PICK(lane, \
A Dskl_watermark_regs.h58 #define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \
A Dintel_combo_phy_regs.h17 #define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
A Dintel_display_regs.h1458 #define _CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
2514 #define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19)
2595 #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5))
2603 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27)
2641 #define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \
/drivers/gpu/drm/i915/
A Di915_reg_defs.h163 #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index]) macro
A Di915_reg.h308 #define HECI_FWSTS(base, x) _MMIO((base) + _PICK(x, -(base), \
990 #define LATENCY_REPORTING_REMOVED(pipe) _PICK((pipe), \
/drivers/gpu/drm/i915/gt/
A Dintel_gt_regs.h321 #define RING_FAULT_REG(engine) _MMIO(_PICK((engine)->class, \

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