| /drivers/net/ethernet/microchip/lan966x/ |
| A D | lan966x_regs.h | 32 #define __REG(...) __VA_ARGS__ macro
35 #define AFI_PORT_FRM_OUT(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 0, 0, 1, 4)
44 #define AFI_PORT_CFG(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 4, 0, 1, 4)
59 #define ANA_ADVLEARN __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 0, 0, 1, 4)
68 #define ANA_VLANMASK __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 8, 0, 1, 4)
71 #define ANA_ANAINTR __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 16, 0, 1, 4)
713 #define DEV_CLOCK_CFG(t) __REG(TARGET_DEV, t, 8, 0, 0, 1, 28, 0, 0, 1, 4)
1130 #define PTP_WF_HIGH_PERIOD(g) __REG(TARGET_PTP,\
1138 #define PTP_WF_LOW_PERIOD(g) __REG(TARGET_PTP,\
1188 #define QS_XTR_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4)
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| /drivers/net/ethernet/microchip/sparx5/ |
| A D | sparx5_main_regs.h | 74 #define __REG(...) __VA_ARGS__ macro
4322 __REG(TARGET_DSM, 0, 1, 0, 0, 1, 4, 0, 0, 1, 4)
5437 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 0, 0, 1, 4)
5472 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 4, 0, 1, 4)
5488 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 8, 0, 1, 4)
7025 __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4)
7047 __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4)
7051 __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4)
7061 __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4)
7071 __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4)
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| /drivers/phy/microchip/ |
| A D | sparx5_serdes_regs.h | 42 #define __REG(...) __VA_ARGS__ macro
1060 __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 36, 0, 1, 4)
1095 __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 44, 0, 1, 4)
1148 __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 48, 0, 1, 4)
1183 __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 52, 0, 1, 4)
1218 __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 56, 0, 1, 4)
1235 __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 76, 0, 1, 4)
1252 __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 96, 0, 1, 4)
2814 __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 0, 0, 1, 4)
2825 __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 4, 0, 1, 4)
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| A D | lan966x_serdes_regs.h | 15 #define __REG(...) __VA_ARGS__ macro
18 #define HSIO_SD_CFG(g) __REG(TARGET_HSIO, 0, 1, 8, g, 3, 32, 0, 0, 1, 4)
111 #define HSIO_MPLL_CFG(g) __REG(TARGET_HSIO, 0, 1, 8, g, 3, 32, 8, 0, 1, 4)
138 #define HSIO_SD_STAT(g) __REG(TARGET_HSIO, 0, 1, 8, g, 3, 32, 12, 0, 1, 4)
165 #define HSIO_HW_CFG __REG(TARGET_HSIO, 0, 1, 104, 0, 1, 52, 0, 0, 1, 4)
210 #define HSIO_RGMII_CFG(r) __REG(TARGET_HSIO, 0, 1, 104, 0, 1, 52, 20, r, 2, 4)
231 #define HSIO_DLL_CFG(r) __REG(TARGET_HSIO, 0, 1, 104, 0, 1, 52, 36, r, 4, 4)
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| /drivers/net/wireless/mediatek/mt76/mt7915/ |
| A D | regs.h | 126 #define __REG(id) (dev->reg.reg_rev[(id)]) macro
139 #define MT_MCU_INT_EVENT __REG(INT_MCU_CMD_EVENT)
581 #define MT_WFDMA0_BASE __REG(WFDMA0_ADDR)
708 #define MT_INT_SOURCE_CSR __REG(INT_SOURCE_CSR)
709 #define MT_INT_MASK_CSR __REG(INT_MASK_CSR)
712 #define MT_INT1_MASK_CSR __REG(INT1_MASK_CSR)
761 #define MT_MCU_CMD __REG(INT_MCU_CMD_SOURCE)
815 #define MT_CBTOP1_PHY_END __REG(CBTOP1_PHY_END)
1023 #define MT_FW_CIRQ_IDX __REG(FW_CIRQ_IDX_ADDR)
1025 #define MT_FW_TASK_ID __REG(FW_TASK_ID_ADDR)
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