Searched refs:__base (Results 1 – 9 of 9) sorted by relevance
| /drivers/thermal/mediatek/ |
| A D | lvts_thermal.c | 24 #define LVTS_MONCTL0(__base) (__base + 0x0000) argument
25 #define LVTS_MONCTL1(__base) (__base + 0x0004) argument
26 #define LVTS_MONCTL2(__base) (__base + 0x0008) argument
27 #define LVTS_MONINT(__base) (__base + 0x000C) argument
29 #define LVTS_MONIDET0(__base) (__base + 0x0014) argument
33 #define LVTS_H2NTHRE(__base) (__base + 0x0024) argument
34 #define LVTS_HTHRE(__base) (__base + 0x0028) argument
39 #define LVTS_TSSEL(__base) (__base + 0x0040) argument
41 #define LVTS_ID(__base) (__base + 0x004C) argument
47 #define LVTS_MSR0(__base) (__base + 0x0090) argument
[all …]
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| /drivers/clocksource/ |
| A D | timer-nxp-stm.c | 25 #define STM_CR(__base) (__base) argument
32 #define STM_CNT(__base) ((__base) + 0x04) argument
34 #define STM_CCR0(__base) ((__base) + 0x10) argument
35 #define STM_CCR1(__base) ((__base) + 0x20) argument
36 #define STM_CCR2(__base) ((__base) + 0x30) argument
37 #define STM_CCR3(__base) ((__base) + 0x40) argument
41 #define STM_CIR0(__base) ((__base) + 0x14) argument
42 #define STM_CIR1(__base) ((__base) + 0x24) argument
43 #define STM_CIR2(__base) ((__base) + 0x34) argument
44 #define STM_CIR3(__base) ((__base) + 0x44) argument
[all …]
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| /drivers/watchdog/ |
| A D | s32g_wdt.c | 20 #define S32G_SWT_CR(__base) ((__base) + 0x00) /* Control Register offset */ argument
26 #define S32G_SWT_TO(__base) ((__base) + 0x08) /* Timeout Register offset */ argument
28 #define S32G_SWT_SR(__base) ((__base) + 0x10) /* Service Register offset */ argument
32 #define S32G_SWT_CO(__base) ((__base) + 0x14) /* Counter output register */ argument
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| /drivers/gpu/drm/vmwgfx/ |
| A D | ttm_object.h | 285 #define ttm_base_object_kfree(__object, __base)\ argument
286 kfree_rcu(__object, __base.rhead)
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| /drivers/net/ethernet/qlogic/qed/ |
| A D | qed.h | 945 #define GET_GTT_REG_ADDR(__base, __offset, __idx) \ argument
946 ((__base) + __offset ## _GTT_OFFSET((__idx)))
948 #define GET_GTT_BDQ_REG_ADDR(__base, __offset, __idx, __bdq_idx) \ argument
949 ((__base) + __offset ## _GTT_OFFSET((__idx), (__bdq_idx)))
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| /drivers/net/wireless/mediatek/mt76/mt7996/ |
| A D | regs.h | 15 struct __base { struct
21 const struct __base *base; argument
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| A D | mmio.c | 20 static const struct __base mt7996_reg_base[] = {
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| /drivers/net/ethernet/amd/ |
| A D | sunlance.c | 277 do { void __iomem *__base = (__lp)->lregs; \
278 sbus_writew(LE_CSR0, __base + RAP); \
279 sbus_writew(LE_C0_STOP, __base + RDP); \
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| /drivers/net/wireless/ralink/rt2x00/ |
| A D | rt2x00queue.c | 1113 #define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \ in rt2x00queue_alloc_entries() argument
1114 (((char *)(__base)) + ((__limit) * (__esize)) + \ in rt2x00queue_alloc_entries()
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