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Searched refs:__display (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/i915/display/
A Dintel_display_device.h144 #define HAS_4TILE(__display) ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14) argument
147 #define HAS_BIGJOINER(__display) (DISPLAY_VER(__display) >= 11 && HAS_DSC(__display)) argument
151 #define HAS_CMTG(__display) (!(__display)->platform.dg2 && DISPLAY_VER(__display) >= 13) argument
152 #define HAS_CUR_FBC(__display) (!HAS_GMCH(__display) && IS_DISPLAY_VER(__display, 7, 13)) argument
162 #define HAS_DP20(__display) ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14) argument
163 #define HAS_DPT(__display) (DISPLAY_VER(__display) >= 13) argument
167 #define HAS_DSC_3ENGINES(__display) (DISPLAY_VERx100(__display) == 1401 && HAS_DSC(__display)) argument
168 #define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >= 12 && HAS_DSC(__display)) argument
176 #define HAS_FDI(__display) (IS_DISPLAY_VER((__display), 5, 8) && !HAS_GMCH(__display)) argument
178 #define HAS_HW_SAGV_WM(__display) (DISPLAY_VER(__display) >= 13 && !(__display)->platform.dgfx) argument
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A Dintel_gmbus_regs.h11 #define __GMBUS_MMIO_BASE(__display) ((__display)->gmbus.mmio_base) argument
13 #define GPIO(__display, gpio) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5010 + 4 * (gpio)) argument
30 #define GMBUS0(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5100) argument
40 #define GMBUS1(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5104) argument
57 #define GMBUS2(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5108) argument
67 #define GMBUS3(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x510c) argument
70 #define GMBUS4(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5110) argument
78 #define GMBUS5(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5120) argument
A Dintel_display_rpm.h15 #define __with_intel_display_rpm(__display, __wakeref) \ argument
16 for (struct ref_tracker *(__wakeref) = intel_display_rpm_get(__display); (__wakeref); \
17 intel_display_rpm_put((__display), (__wakeref)), (__wakeref) = NULL)
19 #define with_intel_display_rpm(__display) \ argument
20 __with_intel_display_rpm((__display), __UNIQUE_ID(wakeref))
A Dintel_dpll_mgr.h33 #define for_each_dpll(__display, __pll, __i) \ argument
34 for ((__i) = 0; (__i) < (__display)->dpll.num_dpll && \
35 ((__pll) = &(__display)->dpll.dplls[(__i)]) ; (__i)++)
A Dintel_combo_phy.c15 #define for_each_combo_phy(__display, __phy) \ argument
17 for_each_if(intel_phy_is_combo(__display, __phy))
19 #define for_each_combo_phy_reverse(__display, __phy) \ argument
21 for_each_if(intel_phy_is_combo(__display, __phy))
A Dintel_display.h552 #define INTEL_DISPLAY_STATE_WARN(__display, condition, format...) ({ \ argument
555 if (!drm_WARN((__display)->drm, (__display)->params.verbose_state_checks, format)) \
556 drm_err((__display)->drm, format); \
A Dintel_fbc.c68 #define for_each_fbc_id(__display, __fbc_id) \ argument
70 for_each_if(DISPLAY_RUNTIME_INFO(__display)->fbc_mask & BIT(__fbc_id))
72 #define for_each_intel_fbc(__display, __fbc, __fbc_id) \ argument
73 for_each_fbc_id((__display), (__fbc_id)) \
74 for_each_if((__fbc) = (__display)->fbc[(__fbc_id)])
A Dintel_display_power.c35 #define for_each_power_domain_well(__display, __power_well, __domain) \ argument
36 for_each_power_well((__display), __power_well) \
39 #define for_each_power_domain_well_reverse(__display, __power_well, __domain) \ argument
40 for_each_power_well_reverse((__display), __power_well) \
A Dintel_display_regs.h2860 #define VLV_PIPE_MSA_MISC(__display, pipe) \ argument
2861 _MMIO_PIPE2(__display, pipe, _VLV_PIPE_MSA_MISC_A)
A Dintel_hdcp.c38 #define USE_HDCP_GSC(__display) (DISPLAY_VER(__display) >= 14) argument

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