Home
last modified time | relevance | path

Searched refs:__reg (Results 1 – 25 of 27) sorted by relevance

12

/drivers/net/wireless/ralink/rt2x00/
A Drt2x00reg.h235 #define SET_FIELD(__reg, __type, __field, __value)\ argument
238 *(__reg) &= ~((__field).bit_mask); \
239 *(__reg) |= ((__value) << \
244 #define GET_FIELD(__reg, __type, __field) \ argument
247 ((__reg) & ((__field).bit_mask)) >> \
253 #define rt2x00_get_field32(__reg, __field) \ argument
254 GET_FIELD(__reg, struct rt2x00_field32, __field)
258 #define rt2x00_get_field16(__reg, __field) \ argument
259 GET_FIELD(__reg, struct rt2x00_field16, __field)
263 #define rt2x00_get_field8(__reg, __field) \ argument
[all …]
A Drt2400pci.c40 #define WAIT_FOR_BBP(__dev, __reg) \ argument
41 rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
42 #define WAIT_FOR_RF(__dev, __reg) \ argument
43 rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
A Drt2500usb.c117 #define WAIT_FOR_BBP(__dev, __reg) \ argument
118 rt2500usb_regbusy_read((__dev), PHY_CSR8, PHY_CSR8_BUSY, (__reg))
119 #define WAIT_FOR_RF(__dev, __reg) \ argument
120 rt2500usb_regbusy_read((__dev), PHY_CSR10, PHY_CSR10_RF_BUSY, (__reg))
A Drt61pci.c46 #define WAIT_FOR_BBP(__dev, __reg) \ argument
47 rt2x00mmio_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
48 #define WAIT_FOR_RF(__dev, __reg) \ argument
49 rt2x00mmio_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
50 #define WAIT_FOR_MCU(__dev, __reg) \ argument
52 H2M_MAILBOX_CSR_OWNER, (__reg))
A Drt2500pci.c40 #define WAIT_FOR_BBP(__dev, __reg) \ argument
41 rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
42 #define WAIT_FOR_RF(__dev, __reg) \ argument
43 rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
A Drt73usb.c47 #define WAIT_FOR_BBP(__dev, __reg) \ argument
48 rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
49 #define WAIT_FOR_RF(__dev, __reg) \ argument
50 rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
/drivers/pmdomain/amlogic/
A Dmeson-ee-pwrc.c129 #define VPU_MEMPD(__reg) \ argument
130 { __reg, GENMASK(1, 0) }, \
145 { __reg, GENMASK(31, 30) }
148 { __reg, BIT(8) }, \
149 { __reg, BIT(9) }, \
150 { __reg, BIT(10) }, \
151 { __reg, BIT(11) }, \
152 { __reg, BIT(12) }, \
153 { __reg, BIT(13) }, \
154 { __reg, BIT(14) }, \
[all …]
/drivers/mmc/host/
A Ddw_mmc.h469 #define mci_fifo_readw(__reg) __raw_readw(__reg) argument
470 #define mci_fifo_readl(__reg) __raw_readl(__reg) argument
471 #define mci_fifo_readq(__reg) __raw_readq(__reg) argument
473 #define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value) argument
474 #define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value) argument
475 #define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value) argument
534 #define __raw_writeq(__value, __reg) \ argument
535 (*(volatile u64 __force *)(__reg) = (__value))
536 #define __raw_readq(__reg) (*(volatile u64 __force *)(__reg)) argument
/drivers/media/dvb-frontends/
A Dstv090x_priv.h37 #define STV090x_READ_DEMOD(__state, __reg) (( \ argument
39 stv090x_read_reg(__state, STV090x_P2_##__reg) : \
40 stv090x_read_reg(__state, STV090x_P1_##__reg))
42 #define STV090x_WRITE_DEMOD(__state, __reg, __data) (( \ argument
44 stv090x_write_reg(__state, STV090x_P2_##__reg, __data) :\
45 stv090x_write_reg(__state, STV090x_P1_##__reg, __data))
/drivers/gpu/drm/armada/
A Darmada_crtc.h20 struct armada_regs *__reg = _r; \
21 __reg[_i].offset = _o; \
22 __reg[_i].mask = ~(_m); \
23 __reg[_i].val = _v; \
/drivers/gpu/drm/i915/display/
A Dintel_dkl_phy_regs.h25 #define DKL_REG_TC_PORT(__reg) \ argument
26 (TC_PORT_1 + ((__reg).reg - _DKL_PHY1_BASE) / (_DKL_PHY2_BASE - _DKL_PHY1_BASE))
29 #define DKL_REG_MMIO(__reg) _MMIO((__reg).reg) argument
/drivers/clk/microchip/
A Dclk-pic32mzda.c27 #define DECLARE_PERIPHERAL_CLOCK(__clk_name, __reg, __flags) \ argument
29 .ctrl_reg = (__reg), \
41 #define DECLARE_REFO_CLOCK(__clkid, __reg) \ argument
43 .ctrl_reg = (__reg), \
/drivers/gpu/drm/xe/regs/
A Dxe_reg_defs.h72 struct xe_reg __reg; member
129 .__reg = XE_REG_INITIALIZER(r_, ##__VA_ARGS__, .mcr = 1) \
/drivers/fsi/
A Dfsi-master-hub.c200 __be32 __reg; in hub_master_probe() local
203 rc = fsi_device_read(fsi_dev, FSI_MVER, &__reg, sizeof(__reg)); in hub_master_probe()
207 reg = be32_to_cpu(__reg); in hub_master_probe()
/drivers/net/ethernet/qlogic/qed/
A Dqed_init_fw_funcs.c175 u32 __reg = 0; \
177 BUILD_BUG_ON(sizeof((map).reg) != sizeof(__reg)); \
179 SET_FIELD(__reg, QM_RF_PQ_MAP_PQ_VALID, 1); \
180 SET_FIELD(__reg, QM_RF_PQ_MAP_RL_VALID, \
182 SET_FIELD(__reg, QM_RF_PQ_MAP_VP_PQ_ID, (vp_pq_id)); \
183 SET_FIELD(__reg, QM_RF_PQ_MAP_RL_ID, (rl_id)); \
184 SET_FIELD(__reg, QM_RF_PQ_MAP_VOQ, (ext_voq)); \
185 SET_FIELD(__reg, QM_RF_PQ_MAP_WRR_WEIGHT_GROUP, \
189 __reg); \
190 (map).reg = cpu_to_le32(__reg); \
/drivers/net/ethernet/cadence/
A Dmacb.h797 #define macb_or_gem_writel(__bp, __reg, __value) \ argument
800 gem_writel((__bp), __reg, __value); \
802 macb_writel((__bp), __reg, __value); \
805 #define macb_or_gem_readl(__bp, __reg) \ argument
809 __v = gem_readl((__bp), __reg); \
811 __v = macb_readl((__bp), __reg); \
/drivers/net/ethernet/smsc/
A Dsmc91x.h35 unsigned int __reg = (r); \
36 SMC_outb(__val16, a, __reg); \
37 SMC_outb(__val16 >> 8, a, __reg + (1 << SMC_IO_SHIFT)); \
43 unsigned int __reg = r; \
44 __val16 = SMC_inb(a, __reg); \
45 __val16 |= SMC_inb(a, __reg + (1 << SMC_IO_SHIFT)) << 8; \
/drivers/media/platform/samsung/s3c-camif/
A Dcamif-regs.h159 #define CISTATUS_FRAMECNT(__reg) (((__reg) >> 26) & 0x3) argument
/drivers/pinctrl/spear/
A Dpinctrl-plgpio.c667 #define plgpio_prepare_reg(__reg, _off, _mask, _tmp) \ argument
669 regmap_read(plgpio->regmap, plgpio->regs.__reg + _off, &_tmp); \
671 plgpio->csave_regs[i].__reg = \
672 _tmp | (plgpio->csave_regs[i].__reg & _mask); \
/drivers/net/ethernet/sun/
A Dsunhme.c208 #define hme_write32(__hp, __reg, __val) \ argument
209 ((__hp)->write32((__reg), (__val)))
210 #define hme_read32(__hp, __reg) \ argument
211 ((__hp)->read32(__reg))
221 #define hme_write32(__hp, __reg, __val) \ argument
222 sbus_writel((__val), (__reg))
223 #define hme_read32(__hp, __reg) \ argument
224 sbus_readl(__reg)
239 writel((__val), (__reg))
240 #define hme_read32(__hp, __reg) \ argument
[all …]
/drivers/gpu/drm/xe/
A Dxe_reg_sr.c126 return (const struct xe_reg_mcr){.__reg.raw = reg.raw }; in to_xe_reg_mcr()
A Dxe_gt_mcr.c53 return reg_mcr.__reg; in to_xe_reg()
/drivers/hwmon/
A Dadt7411.c199 #define ADT7411_BIT_ATTR(__name, __reg, __bit) \ argument
201 adt7411_set_bit, __bit, __reg)
/drivers/thermal/mediatek/
A Dlvts_thermal.c175 #define LVTS_DEBUG_FS_REGS(__reg) \ argument
177 .name = __stringify(__reg), \
178 .offset = __reg(0), \
/drivers/gpu/drm/i915/
A Dintel_uncore.c917 u32 __reg = (reg); \
918 __reg < 0x40000 || __reg >= 0x116000; \

Completed in 871 milliseconds

12