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/drivers/staging/iio/frequency/
A Ddds.h16 _mode, _show, _store, _addr)
31 _mode, _show, _store, _addr)
39 _mode, _show, _store, _addr)
54 _mode, _show, _store, _addr)
62 _mode, _show, _store, _addr)
70 _mode, _show, _store, _addr)
78 _mode, _show, _store, _addr)
86 _mode, _show, _store, _addr)
93 _mode, _show, _store, _addr) \ argument
95 _mode, _show, _store, _addr)
[all …]
/drivers/gpu/drm/nouveau/include/nvkm/core/
A Dmemory.h79 u32 _addr = (a), _data = nvkm_ro32((o), _addr); \
80 nvkm_wo32((o), _addr, (_data & ~(m)) | (d)); \
91 u32 _addr = (a), _size = (s) >> 2, *_data = (void *)(p); \
93 *(_data++) = nvkm_ro32((o), _addr); \
94 _addr += 4; \
99 u32 _addr = (a), _size = (s) >> 2, *_data = (void *)(p); \
101 nvkm_wo32((o), _addr, *(_data++)); \
102 _addr += 4; \
A Ddevice.h132 u32 _addr = (a), _temp = nvkm_rd32(_device, _addr); \
133 nvkm_wr32(_device, _addr, (_temp & ~(m)) | (v)); \
/drivers/iio/adc/
A Dltc2497-core.c108 #define LTC2497_CHAN(_chan, _addr, _ds_name) { \ argument
112 .address = (_addr | (_chan / 2) | ((_chan & 1) ? LTC2497_SIGN : 0)), \
118 #define LTC2497_CHAN_DIFF(_chan, _addr) { \ argument
121 .channel = (_chan) * 2 + ((_addr) & LTC2497_SIGN ? 1 : 0), \
122 .channel2 = (_chan) * 2 + ((_addr) & LTC2497_SIGN ? 0 : 1),\
123 .address = (_addr | _chan), \
A Dltc2309.c63 #define LTC2309_CHAN(_chan, _addr) { \ argument
66 .address = _addr, \
72 #define LTC2309_DIFF_CHAN(_chan, _chan2, _addr) { \ argument
76 .address = _addr, \
A Dxilinx-ams.c225 #define AMS_CHAN_TEMP(_scan_index, _addr, _name) { \ argument
228 .address = (_addr), \
241 .address = (_addr), \
250 #define AMS_PS_CHAN_TEMP(_scan_index, _addr, _name) \ argument
251 AMS_CHAN_TEMP(PS_SEQ(_scan_index), _addr, _name)
252 #define AMS_PS_CHAN_VOLTAGE(_scan_index, _addr, _name) \ argument
253 AMS_CHAN_VOLTAGE(PS_SEQ(_scan_index), _addr, true, _name)
255 #define AMS_PL_CHAN_TEMP(_scan_index, _addr, _name) \ argument
256 AMS_CHAN_TEMP(PL_SEQ(_scan_index), _addr, _name)
258 AMS_CHAN_VOLTAGE(PL_SEQ(_scan_index), _addr, _alarm, _name)
[all …]
A Dxilinx-xadc-core.c1056 #define XADC_CHAN_TEMP(_chan, _scan_index, _addr, _bits) { \ argument
1060 .address = (_addr), \
1081 .address = (_addr), \
1089 .sign = ((_addr) == XADC_REG_VREFN) ? 's' : 'u', \
1099 #define XADC_7S_CHAN_TEMP(_chan, _scan_index, _addr) \ argument
1100 XADC_CHAN_TEMP(_chan, _scan_index, _addr, 12)
1101 #define XADC_7S_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) \ argument
1102 XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, 12, _ext, _alarm)
1134 #define XADC_US_CHAN_TEMP(_chan, _scan_index, _addr) \ argument
1135 XADC_CHAN_TEMP(_chan, _scan_index, _addr, 10)
[all …]
A Dti-ads1015.c183 #define ADS1015_V_CHAN(_chan, _addr, _realbits, _shift, _event_spec, _num_event_specs) { \ argument
186 .address = _addr, \
194 .scan_index = _addr, \
207 #define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr, _realbits, _shift, _event_spec, _num_event_specs)… argument
211 .address = _addr, \
220 .scan_index = _addr, \
A Dmt6370-adc.c262 #define MT6370_ADC_CHAN(_idx, _type, _addr, _extra_info) { \ argument
265 .address = _addr, \
A Dti-ads7924.c122 #define ADS7924_V_CHAN(_chan, _addr) { \ argument
126 .address = _addr, \
/drivers/net/ethernet/hisilicon/hibmcge/
A Dhbg_hw.h39 typeof(addr) _addr = (addr); \
40 u32 _value = hbg_reg_read(_priv, _addr); \
42 hbg_reg_write(_priv, _addr, _value); })
/drivers/iio/pressure/
A Dzpa2326_i2c.c32 #define ZPA2326_SA0(_addr) (_addr & BIT(0)) in zpa2326_i2c_hwid() argument
/drivers/gpu/drm/nouveau/include/nvif/
A Dobject.h62 u32 _addr = (b), _data = nvif_rd32(__object, _addr); \
63 nvif_wr32(__object, _addr, (_data & ~(c)) | (d)); \
/drivers/net/wireless/realtek/rtw89/
A Dphy.h758 #define RTW89_DECL_RFK_WRF(_path, _addr, _mask, _data) \ argument
761 .addr = _addr, \
765 #define RTW89_DECL_RFK_WM(_addr, _mask, _data) \ argument
767 .addr = _addr, \
771 #define RTW89_DECL_RFK_WS(_addr, _mask) \ argument
773 .addr = _addr, \
776 #define RTW89_DECL_RFK_WC(_addr, _mask) \ argument
778 .addr = _addr, \
/drivers/net/ethernet/brocade/bna/
A Dbna.h29 #define BNA_SET_DMA_ADDR(_addr, _bna_dma_addr) \ argument
32 cpu_to_be64((u64)(_addr)); \
41 #define BNA_GET_DMA_ADDR(_bna_dma_addr, _addr) \ argument
43 (_addr) = ((((u64)ntohl((_bna_dma_addr)->msb))) << 32) \
/drivers/iio/dac/
A Drohm-bd79703.c87 #define BD79703_CHAN_ADDR(_chan, _addr) { \ argument
94 .address = (_addr), \
/drivers/dma/amd/qdma/
A Dqdma.h39 #define QDMA_INTR_RING_BASE(_addr) ((_addr) >> 12) argument
/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
A Dvmm.h322 u64 _addr = ((BASE) + MAP->off); \
334 FILL(VMM, PT, PTEI, _ptes, MAP, _addr); \
372 const u64 _addr = (m)->addr + _pteo; \
373 VMM_SPAM((v), " %010llx %016llx%016llx"f, _addr, (hi), (lo), ##a); \
/drivers/iio/light/
A Dcm3323.c52 #define CM3323_COLOR_CHANNEL(_color, _addr) { \ argument
58 .address = _addr, \
A Dtcs3414.c63 #define TCS3414_CHANNEL(_color, _si, _addr) { \ argument
70 .address = _addr, \
A Dtcs3472.c91 #define TCS3472_CHANNEL(_color, _si, _addr) { \ argument
98 .address = _addr, \
/drivers/iio/chemical/
A Dpms7003.c173 #define PMS7003_CHAN(_index, _mod, _addr) { \ argument
177 .address = _addr, \
/drivers/usb/gadget/udc/
A Dpxa27x_udc.h263 #define PXA_EP_DEF(_idx, _addr, dir, _type, maxpkt, _config, iface, altset) \ argument
268 .dir_in = dir, .addr = _addr, \
/drivers/iio/accel/
A Dmxc4005.c300 #define MXC4005_CHANNEL(_axis, _addr) { \ argument
304 .address = _addr, \
/drivers/mfd/
A Dmt6360-core.c77 #define I2C_ADDR_XLATE_8BIT(_addr, _rw) (((_addr & 0x7F) << 1) + _rw) argument

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