| /drivers/reset/sti/ |
| A D | reset-stih407.c | 18 #define STIH407_PDN_0(_bit) \ argument
19 _SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit)
20 #define STIH407_PDN_1(_bit) \ argument
21 _SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit)
22 #define STIH407_PDN_ETH(_bit, _stat) \ argument
57 #define STIH407_SRST_CORE(_reg, _bit) \ argument
58 _SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit)
60 #define STIH407_SRST_SBC(_reg, _bit) \ argument
61 _SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit)
63 #define STIH407_SRST_LPM(_reg, _bit) \ argument
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| /drivers/clk/meson/ |
| A D | clk-regmap.h | 121 #define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ argument
125 .bit_idx = (_bit), \
136 #define MESON_PCLK(_name, _reg, _bit, _pname) \ argument
137 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname)
139 #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ argument
140 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname)
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| A D | gxbb-aoclk.c | 26 #define GXBB_AO_GATE(_name, _bit) \ argument
30 .bit_idx = (_bit), \
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| A D | c3-peripherals.c | 167 #define C3_CLK_GATE(_name, _reg, _bit, _fw_name, _ops, _flags) \ argument
171 .bit_idx = (_bit), \
184 #define C3_SYS_GATE(_name, _reg, _bit, _flags) \ argument
185 C3_CLK_GATE(_name, _reg, _bit, sysclk, \
188 #define C3_SYS_GATE_RO(_name, _reg, _bit) \ argument
189 C3_CLK_GATE(_name, _reg, _bit, sysclk, \
293 #define C3_AXI_GATE(_name, _reg, _bit, _flags) \ argument
294 C3_CLK_GATE(_name, _reg, _bit, axiclk, \
561 #define AML_PWM_CLK_GATE(_name, _reg, _bit) { \ argument
564 .bit_idx = _bit, \
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| A D | axg-aoclk.c | 37 #define AXG_AO_GATE(_name, _bit) \ argument
41 .bit_idx = (_bit), \
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| A D | g12a-aoclk.c | 46 #define AXG_AO_GATE(_name, _reg, _bit) \ argument
50 .bit_idx = (_bit), \
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| A D | axg-audio.c | 80 #define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \ argument
83 .bit_idx = (_bit), \
126 #define AUD_PCLK_GATE(_name, _reg, _bit) { \ argument
129 .bit_idx = (_bit), \
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| /drivers/clk/renesas/ |
| A D | rzg2l-cpg.h | 221 #define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, _is_coupled) \ argument
228 .bit = (_bit), \
232 #define DEF_MOD(_name, _id, _parent, _off, _bit, _mstop_conf) \ argument
233 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, false)
235 #define DEF_COUPLED(_name, _id, _parent, _off, _bit, _mstop_conf) \ argument
236 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, true)
251 #define DEF_RST_MON(_id, _off, _bit, _monbit) \ argument
254 .bit = (_bit), \
257 #define DEF_RST(_id, _off, _bit) \ argument
258 DEF_RST_MON(_id, _off, _bit, -1)
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| A D | rzv2h-cpg.h | 108 #define FIXED_MOD_CONF_PACK(_index, _bit) \ argument
111 .mon_bit = (_bit), \
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| /drivers/pinctrl/mediatek/ |
| A D | pinctrl-mtk-common.h | 109 #define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \ argument
113 .bit = _bit, \
157 #define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \ argument
161 .bit = _bit, \
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| A D | pinctrl-mt2701.c | 30 #define MTK_PINMUX_SPEC(_pin, _offset, _bit) \ argument
34 .bit = _bit, \
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| /drivers/clk/bcm/ |
| A D | clk-kona.h | 91 #define POLICY(_offset, _bit) \ argument
94 .bit = (_bit), \
375 #define TRIGGER(_offset, _bit) \ argument
378 .bit = (_bit), \
434 #define CCU_LVM_EN(_offset, _bit) \ argument
437 .bit = (_bit), \
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| /drivers/net/ethernet/mellanox/mlx5/core/steering/hws/ |
| A D | internal.h | 36 #define IS_BIT_SET(_value, _bit) ((_value) & (1ULL << (_bit))) argument
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| /drivers/clk/mvebu/ |
| A D | armada-37xx-periph.c | 129 #define PERIPH_GATE(_name, _bit) \ argument
132 .bit_idx = _bit, \
181 #define PERIPH_CLK_FULL_DD(_name, _bit, _shift, _reg1, _reg2, _shift1, _shift2)\ argument
182 static PERIPH_GATE(_name, _bit); \
186 #define PERIPH_CLK_FULL(_name, _bit, _shift, _reg, _shift1, _table) \ argument
187 static PERIPH_GATE(_name, _bit); \
191 #define PERIPH_CLK_GATE_DIV(_name, _bit, _reg, _shift, _table) \ argument
192 static PERIPH_GATE(_name, _bit); \
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| /drivers/reset/ |
| A D | reset-uniphier.c | 27 #define UNIPHIER_RESET(_id, _reg, _bit) \ argument
31 .bit = (_bit), \
34 #define UNIPHIER_RESETX(_id, _reg, _bit) \ argument
38 .bit = (_bit), \
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| /drivers/clk/uniphier/ |
| A D | clk-uniphier.h | 95 #define UNIPHIER_CLK_GATE(_name, _idx, _parent, _reg, _bit) \ argument
103 .bit = (_bit), \
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| /drivers/net/wireless/realtek/rtlwifi/rtl8192se/ |
| A D | fw.h | 318 #define FW_CMD_IO_CLR(rtlpriv, _bit) \ argument
321 rtlpriv->rtlhal.fwcmd_iomap &= (~_bit); \
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| /drivers/staging/rtl8723bs/hal/ |
| A D | odm_interface.h | 38 #define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit)
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| /drivers/clk/ |
| A D | clk-k210.c | 49 #define K210_GATE(_reg, _bit) \ argument
51 .gate_bit = (_bit)
59 #define K210_MUX(_reg, _bit) \ argument
61 .mux_bit = (_bit)
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| /drivers/memory/tegra/ |
| A D | tegra114.c | 1076 #define TEGRA114_MC_RESET(_name, _control, _status, _bit) \ argument
1082 .bit = _bit, \
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| A D | tegra20.c | 251 #define TEGRA20_MC_RESET(_name, _control, _status, _reset, _bit) \ argument
258 .bit = _bit, \
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| A D | tegra124.c | 1112 #define TEGRA124_MC_RESET(_name, _control, _status, _bit) \ argument
1118 .bit = _bit, \
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| A D | tegra210.c | 1234 #define TEGRA210_MC_RESET(_name, _control, _status, _bit) \ argument
1240 .bit = _bit, \
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| A D | tegra30.c | 1189 #define TEGRA30_MC_RESET(_name, _control, _status, _bit) \ argument
1195 .bit = _bit, \
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| /drivers/platform/cznic/ |
| A D | turris-omnia-mcu-gpio.c | 88 #define _DEF_GPIO(_cmd, _ctl_cmd, _bit, _ctl_bit, _int_bit, _feat, _feat_mask) \ argument
92 .bit = _bit, \
|