Searched refs:_clk (Results 1 – 7 of 7) sorted by relevance
| /drivers/clk/stm32/ |
| A D | clk-stm32-core.h | 163 #define STM32_CLOCK_CFG(_binding, _clk, _sec_id, _struct, _register)\ argument
167 .clock_cfg = (_struct) {_clk},\
171 #define STM32_MUX_CFG(_binding, _clk, _sec_id)\ argument
172 STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_mux *,\
175 #define STM32_GATE_CFG(_binding, _clk, _sec_id)\ argument
176 STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_gate *,\
179 #define STM32_DIV_CFG(_binding, _clk, _sec_id)\ argument
180 STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_div *,\
183 #define STM32_COMPOSITE_CFG(_binding, _clk, _sec_id)\ argument
184 STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_composite *,\
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| /drivers/clk/qcom/ |
| A D | clk-rpm.c | 36 static struct clk_rpm clk_rpm_##_name##_clk = { \
49 .peer = &clk_rpm_##_name##_clk, \
61 static struct clk_rpm clk_rpm_##_name##_clk = { \
73 static struct clk_rpm clk_rpm_##_name##_clk = { \
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| A D | clk-smd-rpm.c | 109 __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \
114 _name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \
119 _name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \
129 _name##_clk, _name##_a_clk, \
138 __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \
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| /drivers/cpufreq/ |
| A D | rcpufreq_dt.rs | 48 _clk: Clk, field
149 _clk: clk, in init()
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| /drivers/ufs/host/ |
| A D | ufs-exynos.c | 534 unsigned long clk = 0, _clk, clk_period; in exynos_ufs_calc_pwm_clk_div() local
539 _clk = NSEC_PER_SEC * mult / (clk_period * divs[i] * div); in exynos_ufs_calc_pwm_clk_div()
540 if (_clk >= pwm_min && _clk <= pwm_max) { in exynos_ufs_calc_pwm_clk_div()
541 if (_clk > clk) { in exynos_ufs_calc_pwm_clk_div()
543 clk = _clk; in exynos_ufs_calc_pwm_clk_div()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| A D | gm20b.c | 852 struct gm20b_clk *_clk = gm20b_clk(base); in gm20b_clk_init() local
856 _clk->uv = nvkm_volt_get(volt); in gm20b_clk_init()
859 ret = gm20b_clk_init_dvfs(_clk); in gm20b_clk_init()
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| /drivers/clk/renesas/ |
| A D | r9a06g032-clocks.c | 165 #define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) { \ argument
166 .gate = _clk, \
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