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Searched refs:_div_reg (Results 1 – 3 of 3) sorted by relevance

/drivers/clk/sophgo/
A Dclk-cv18xx-ip.h78 _div_reg, _div_shift, _div_width, _div_init, \ argument
85 .div = CV1800_CLK_REG(_div_reg, _div_shift, \
106 _div_reg, _div_shift, _div_width, _div_init, \ argument
110 _div_reg, _div_shift, _div_width, _div_init,\
114 _div_reg, _div_shift, _div_width, _div_init, \ argument
119 _div_reg, _div_shift, \
147 _div_reg, _div_shift, _div_width, _div_init, \ argument
156 .div = CV1800_CLK_REG(_div_reg, _div_shift, \
164 _div_reg, _div_shift, _div_width, _div_init, \ argument
174 _div_reg, _div_shift, _div_width, _div_init, \ argument
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/drivers/clk/mediatek/
A Dclk-mtk.h162 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \ argument
167 .divider_reg = _div_reg, \
/drivers/clk/
A Dclk-bm1880.c143 #define GATE_DIV(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \ argument
151 .div_reg = _div_reg, \

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