| /drivers/clk/sprd/ |
| A D | gate.h | 32 _sc_offset, _enable_mask, _flags, \ argument
43 _ops, _flags), \
61 _enable_mask, _flags, _gate_flags) \ argument
83 _flags, _gate_flags, \ argument
91 _sc_offset, _enable_mask, _flags, \ argument
95 _flags, _gate_flags, 0, _ops)
101 _sc_offset, _enable_mask, _flags, \
111 _sc_offset, _enable_mask, _flags, \ argument
120 _enable_mask, _flags, \ argument
132 _enable_mask, _flags, \
[all …]
|
| A D | composite.h | 23 _dwidth, _flags, _fn) \ argument
31 &sprd_comp_ops, _flags), \
39 _dwidth, _flags, CLK_HW_INIT_PARENTS)
48 _dwidth, _flags) \ argument
51 _dwidth, _flags, \
55 _mwidth, _dshift, _dwidth, _flags) \ argument
58 _flags)
63 _flags) \ argument
66 _dwidth, _flags, \
71 _dwidth, _flags) \ argument
[all …]
|
| A D | mux.h | 40 _reg, _shift, _width, _flags, _fn) \ argument
47 &sprd_mux_ops, _flags), \
52 _reg, _shift, _width, _flags) \ argument
54 _reg, _shift, _width, _flags, \
58 _shift, _width, _flags) \ argument
60 _reg, _shift, _width, _flags)
63 _reg, _shift, _width, _flags) \ argument
65 _reg, _shift, _width, _flags, \
69 _shift, _width, _flags) \ argument
71 _reg, _shift, _width, _flags)
|
| A D | div.h | 41 _shift, _width, _flags, _fn) \ argument
48 &sprd_div_ops, _flags), \
53 _shift, _width, _flags) \ argument
55 _shift, _width, _flags, CLK_HW_INIT)
58 _shift, _width, _flags) \ argument
60 _shift, _width, _flags, CLK_HW_INIT_FW_NAME)
63 _shift, _width, _flags) \ argument
65 _shift, _width, _flags, CLK_HW_INIT_HW)
|
| /drivers/clk/sunxi-ng/ |
| A D | ccu_div.h | 47 .flags = _flags, \
109 _flags)
122 _flags), \
173 _gate, _flags)
183 _gate, _flags)
192 0, _flags)
211 _flags) \ argument
235 _flags) \ argument
253 _flags), \
259 _flags) \ argument
[all …]
|
| A D | ccu_mp.h | 51 _flags), \
73 _flags), \
92 _flags), \
100 _flags) \ argument
105 0, _flags)
112 _flags) \ argument
126 _flags), \
146 _flags), \
177 _flags) \ argument
182 0, _flags)
[all …]
|
| A D | ccu_gate.h | 19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
27 _flags), \
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
39 _flags), \
51 _flags), \
67 _flags), \
72 _gate, _prediv, _flags) \ argument
82 _flags), \
95 _flags), \
100 _gate, _prediv, _flags) \ argument
[all …]
|
| A D | ccu_mux.h | 51 _flags, _features) \ argument
60 _flags), \
67 _width, _gate, _flags) \ argument
70 _width, _gate, _flags, \
75 _flags) \ argument
78 _width, _gate, _flags, 0)
84 _flags)
87 _flags) \ argument
101 _flags), \
108 _shift, _width, 0, _flags)
[all …]
|
| A D | ccu_nm.h | 43 _gate, _lock, _flags) \ argument
57 _flags), \
66 _gate, _lock, _flags) \ argument
81 _flags), \
107 _flags), \
119 _gate, _lock, _flags, \ argument
137 _flags), \
149 _gate, _lock, _flags) \ argument
158 _gate, _lock, _flags, \
178 _gate, _lock, _flags, \
[all …]
|
| A D | ccu_nkm.h | 41 _gate, _lock, _flags) \ argument
54 _flags), \
62 _gate, _lock, _flags) \ argument
74 _flags), \
|
| /drivers/clk/spacemit/ |
| A D | ccu_mix.h | 57 .flags = _flags, \
91 _flags), \
105 _mul, _flags) \ argument
121 _mask_gate, _flags) \ argument
133 _mask_gate, _flags) \ argument
140 _flags), \
159 _muxwidth, _mask_gate, _flags) \ argument
175 _flags) \ argument
178 _mask_gate, _flags)
195 _muxwidth, _flags) \ argument
[all …]
|
| A D | ccu_ddn.h | 23 #define CCU_DDN_INIT(_name, _parent, _flags) \ argument
24 CLK_HW_INIT_HW(#_name, &_parent.common.hw, &spacemit_ccu_ddn_ops, _flags)
27 _den_shift, _den_width, _flags) \ argument
31 .hw.init = CCU_DDN_INIT(_name, _parent, _flags), \
|
| A D | ccu_pll.h | 57 #define CCU_PLL_HWINIT(_name, _flags) \ argument
63 .flags = _flags, \
67 _mask_lock, _flags) \ argument
73 .hw.init = CCU_PLL_HWINIT(_name, _flags) \
|
| /drivers/clk/sophgo/ |
| A D | clk-cv18xx-ip.h | 73 _flags), \
82 _ops, _flags), \
97 _ops, _flags), \
122 _flags), \
127 _fix_div, _flags) \ argument
136 _flags) \ argument
142 _flags), \
150 _ops, _flags) \ argument
185 _flags), \
202 _flags), \
[all …]
|
| A D | clk-cv18xx-common.h | 20 #define CV1800_CLK_COMMON(_name, _parents, _op, _flags) \ argument
23 _op, _flags), \
51 #define CV1800_CLK_REG(_reg, _shift, _width, _initval, _flags) \ argument
57 .flags = _flags, \
|
| /drivers/clk/actions/ |
| A D | owl-composite.h | 38 _mux, _gate, _div, _flags) \ argument
48 _flags), \
53 _gate, _div, _flags) \ argument
62 _flags), \
67 _mux, _gate, _factor, _flags) \ argument
77 _flags), \
82 _gate, _mul, _div, _flags) \ argument
93 _flags), \
98 _mux, _gate, _flags) \ argument
107 _flags), \
|
| A D | owl-pll.h | 56 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
66 _flags), \
71 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
80 _flags), \
86 _flags) \ argument
95 _flags), \
|
| A D | owl-gate.h | 35 _bit_idx, _gate_flags, _flags) \ argument
43 _flags), \
48 _bit_idx, _gate_flags, _flags) \ argument
55 _flags), \
|
| /drivers/clk/starfive/ |
| A D | clk-starfive-jh71x0.h | 32 #define JH71X0_GATE(_idx, _name, _flags, _parent) \ argument
35 .flags = CLK_SET_RATE_PARENT | (_flags), \
48 #define JH71X0_GDIV(_idx, _name, _flags, _max, _parent) \ argument
51 .flags = _flags, \
64 #define JH71X0__MUX(_idx, _name, _flags, _nparents, ...) \ argument
67 .flags = _flags, \
72 #define JH71X0_GMUX(_idx, _name, _flags, _nparents, ...) \ argument
75 .flags = _flags, \
89 #define JH71X0__GMD(_idx, _name, _flags, _max, _nparents, ...) \ argument
92 .flags = _flags, \
|
| /drivers/net/ethernet/fungible/funcore/ |
| A D | fun_hci.h | 41 .op = (_op), .len8 = (_len8), .flags = cpu_to_be16(_flags), \
159 .subop = (_subop), .flags = cpu_to_be16(_flags), \
535 .subop = (_subop), .flags = (_flags), .nsgl = (_nsgl), \
626 .subop = (_subop), .flags = cpu_to_be16(_flags), \
632 .subop = (_subop), .flags = cpu_to_be16(_flags), \
638 .subop = (_subop), .flags = cpu_to_be16(_flags), \
646 .flags = cpu_to_be16(_flags), .id = cpu_to_be32(_id), \
802 .subop = (_subop), .flags = cpu_to_be16(_flags), \
824 .subop = (_subop), .flags = cpu_to_be16(_flags), \
880 .subop = (_subop), .flags = cpu_to_be16(_flags), \
[all …]
|
| /drivers/gpu/drm/amd/pm/inc/ |
| A D | amdgpu_pm.h | 101 #define __AMDGPU_DEVICE_ATTR(_name, _mode, _show, _store, _flags, ...) \ argument
104 .flags = _flags, \
107 #define AMDGPU_DEVICE_ATTR(_name, _mode, _flags, ...) \ argument
110 _flags, ##__VA_ARGS__)
112 #define AMDGPU_DEVICE_ATTR_RW(_name, _flags, ...) \ argument
114 _flags, ##__VA_ARGS__)
116 #define AMDGPU_DEVICE_ATTR_RO(_name, _flags, ...) \ argument
119 _flags, ##__VA_ARGS__)
|
| /drivers/clk/mediatek/ |
| A D | clk-mux.h | 44 _upd, _flags, _ops) { \ argument
58 .flags = _flags, \
64 _gate, _upd_ofs, _upd, _flags, _ops) \ argument
68 _gate, _upd_ofs, _upd, _flags, _ops) \
72 _width, _gate, _upd_ofs, _upd, _flags, _ops) \ argument
76 _gate, _upd_ofs, _upd, _flags, _ops) \
83 _gate, _upd_ofs, _upd, _flags) \ argument
86 _gate, _upd_ofs, _upd, _flags, \
91 _shift, _width, _gate, _upd_ofs, _upd, _flags) \ argument
94 _shift, _width, _gate, _upd_ofs, _upd, _flags, \
|
| A D | clk-mt7988-infracfg.c | 128 #define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
130 _flags)
132 #define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
134 _flags)
136 #define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
138 _flags)
140 #define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
142 _flags)
|
| A D | clk-mt8183-apmixedsys.c | 24 #define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
26 _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags)
54 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
64 .flags = _flags, \
81 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
86 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
|
| /drivers/net/wireless/ath/ath5k/ |
| A D | ath5k.h | 112 #define AR5K_REG_SM(_val, _flags) \ argument
113 (((_val) << _flags##_S) & (_flags))
116 #define AR5K_REG_MS(_val, _flags) \ argument
117 (((_val) & (_flags)) >> _flags##_S)
124 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ argument
125 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
126 (((_val) << _flags##_S) & (_flags)), _reg)
128 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ argument
130 (_mask)) | (_flags), _reg)
132 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ argument
[all …]
|