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Searched refs:_hw (Results 1 – 25 of 171) sorted by relevance

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/drivers/clk/qcom/
A Dclk-rcg.h113 #define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr) argument
146 #define to_clk_dyn_rcg(_hw) \ argument
147 container_of(to_clk_regmap(_hw), struct clk_dyn_rcg, clkr)
180 #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr) argument
188 #define to_clk_rcg2_gfx3d(_hw) \ argument
189 container_of(to_clk_rcg2(_hw), struct clk_rcg2_gfx3d, rcg)
A Dclk-krait.h24 #define to_krait_mux_clk(_hw) container_of(_hw, struct krait_mux_clk, hw) argument
37 #define to_krait_div2_clk(_hw) container_of(_hw, struct krait_div2_clk, hw) argument
A Dclk-branch.h114 #define to_clk_branch(_hw) \ argument
115 container_of(to_clk_regmap(_hw), struct clk_branch, clkr)
117 #define to_clk_mem_branch(_hw) \ argument
118 container_of(to_clk_branch(_hw), struct clk_mem_branch, branch)
A Dclk-hfpll.h40 #define to_clk_hfpll(_hw) \ argument
41 container_of(to_clk_regmap(_hw), struct clk_hfpll, clkr)
A Dclk-pll.h59 #define to_clk_pll(_hw) container_of(to_clk_regmap(_hw), struct clk_pll, clkr) argument
/drivers/clk/stm32/
A Dclk-stm32-core.h98 #define to_clk_stm32_mux(_hw) container_of(_hw, struct clk_stm32_mux, hw) argument
108 #define to_clk_stm32_gate(_hw) container_of(_hw, struct clk_stm32_gate, hw) argument
118 #define to_clk_stm32_divider(_hw) container_of(_hw, struct clk_stm32_div, hw) argument
130 #define to_clk_stm32_composite(_hw) container_of(_hw, struct clk_stm32_composite, hw) argument
/drivers/net/ethernet/intel/ixgbe/
A Dixgbe_type.h91 #define IXGBE_BY_MAC(_hw, r) ((_hw)->mvals[IXGBE_CAT(r, IDX)]) argument
105 #define IXGBE_I2CCTL(_hw) IXGBE_BY_MAC((_hw), I2CCTL) argument
119 #define IXGBE_EEC(_hw) IXGBE_BY_MAC((_hw), EEC) argument
127 #define IXGBE_FLA(_hw) IXGBE_BY_MAC((_hw), FLA) argument
139 #define IXGBE_GRC(_hw) IXGBE_BY_MAC((_hw), GRC) argument
189 #define IXGBE_I2C_BB_EN(_hw) IXGBE_BY_MAC((_hw), I2C_BB_EN) argument
975 #define IXGBE_FACTPS(_hw) IXGBE_BY_MAC((_hw), FACTPS) argument
983 #define IXGBE_SWSM(_hw) IXGBE_BY_MAC((_hw), SWSM) argument
989 #define IXGBE_FWSM(_hw) IXGBE_BY_MAC((_hw), FWSM) argument
1017 #define IXGBE_CIAA(_hw) IXGBE_BY_MAC((_hw), CIAA) argument
[all …]
/drivers/clk/tegra/
A Dclk.h85 #define to_clk_sync_source(_hw) \ argument
86 container_of(_hw, struct tegra_clk_sync_source, hw)
126 #define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw) argument
385 #define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw) argument
515 #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw) argument
571 #define to_clk_periph_gate(_hw) \ argument
572 container_of(_hw, struct tegra_clk_periph_gate, hw)
628 #define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw) argument
750 #define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw) argument
791 #define to_clk_sdmmc_mux(_hw) container_of(_hw, struct tegra_sdmmc_mux, hw) argument
/drivers/clk/x86/
A Dclk-cgu.c20 #define to_lgm_clk_mux(_hw) container_of(_hw, struct lgm_clk_mux, hw) argument
21 #define to_lgm_clk_divider(_hw) container_of(_hw, struct lgm_clk_divider, hw) argument
22 #define to_lgm_clk_gate(_hw) container_of(_hw, struct lgm_clk_gate, hw) argument
23 #define to_lgm_clk_ddiv(_hw) container_of(_hw, struct lgm_clk_ddiv, hw) argument
/drivers/clk/davinci/
A Dda8xx-cfgchip.c39 #define to_da8xx_cfgchip_gate_clk(_hw) \ argument
40 container_of((_hw), struct da8xx_cfgchip_gate_clk, hw)
210 #define to_da8xx_cfgchip_mux_clk(_hw) \ argument
211 container_of((_hw), struct da8xx_cfgchip_mux_clk, hw)
353 #define to_da8xx_usb0_clk48(_hw) \ argument
354 container_of((_hw), struct da8xx_usb0_clk48, hw)
546 #define to_da8xx_usb1_clk48(_hw) \ argument
547 container_of((_hw), struct da8xx_usb1_clk48, hw)
/drivers/clk/baikal-t1/
A Dccu-pll.h61 #define to_ccu_pll(_hw) container_of(_hw, struct ccu_pll, hw) argument
A Dccu-div.h110 #define to_ccu_div(_hw) container_of(_hw, struct ccu_div, hw) argument
/drivers/clk/
A Dclk-aspeed.h56 #define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw) argument
A Dclk-stm32h7.c429 #define to_timer_ker(_hw) container_of(_hw, struct timer_ker, hw) argument
693 #define to_pll(_hw) container_of(_hw, struct stm32_pll_obj, hw) argument
698 struct clk_hw *_hw = &clk_elem->rgate.gate.hw; in pll_is_enabled() local
700 __clk_hw_set_clk(_hw, hw); in pll_is_enabled()
702 return ready_gate_clk_ops.is_enabled(_hw); in pll_is_enabled()
708 struct clk_hw *_hw = &clk_elem->rgate.gate.hw; in pll_enable() local
710 __clk_hw_set_clk(_hw, hw); in pll_enable()
712 return ready_gate_clk_ops.enable(_hw); in pll_enable()
718 struct clk_hw *_hw = &clk_elem->rgate.gate.hw; in pll_disable() local
720 __clk_hw_set_clk(_hw, hw); in pll_disable()
[all …]
/drivers/clk/microchip/
A Dclk-core.c95 #define clkhw_to_pbclk(_hw) container_of(_hw, struct pic32_periph_clk, hw) argument
245 #define clkhw_to_refosc(_hw) container_of(_hw, struct pic32_ref_osc, hw) argument
589 #define clkhw_to_spll(_hw) container_of(_hw, struct pic32_sys_pll, hw) argument
770 #define clkhw_to_sys_clk(_hw) container_of(_hw, struct pic32_sys_clk, hw) argument
962 #define clkhw_to_sosc(_hw) container_of(_hw, struct pic32_sec_osc, hw) argument
/drivers/clk/ti/
A Dclock.h24 #define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw) argument
37 #define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw) argument
/drivers/clk/ux500/
A Dclk-prcmu.c16 #define to_clk_prcmu(_hw) container_of(_hw, struct clk_prcmu, hw) argument
17 #define to_clk_prcmu_clkout(_hw) container_of(_hw, struct clk_prcmu_clkout, hw) argument
/drivers/clk/spear/
A Dclk-vco-pll.c62 #define to_clk_vco(_hw) container_of(_hw, struct clk_vco, hw) argument
63 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw) argument
/drivers/clk/meson/
A Dvid-pll-div.c58 #define to_meson_vid_pll_div(_hw) \ argument
59 container_of(_hw, struct meson_vid_pll_div, hw)
/drivers/clk/uniphier/
A Dclk-uniphier-gate.c20 #define to_uniphier_clk_gate(_hw) \ argument
21 container_of(_hw, struct uniphier_clk_gate, hw)
A Dclk-uniphier-mux.c21 #define to_uniphier_clk_mux(_hw) container_of(_hw, struct uniphier_clk_mux, hw) argument
A Dclk-uniphier-cpugear.c25 #define to_uniphier_clk_cpugear(_hw) \ argument
26 container_of(_hw, struct uniphier_clk_cpugear, hw)
/drivers/clk/ingenic/
A Dcgu.h220 #define to_ingenic_clk(_hw) container_of(_hw, struct ingenic_clk, hw) argument
/drivers/clk/renesas/
A Drzg2l-cpg.c91 #define to_clk_hw_data(_hw) container_of(_hw, struct clk_hw_data, hw) argument
103 #define to_sd_mux_hw_data(_hw) container_of(_hw, struct sd_mux_hw_data, hw_data) argument
121 #define to_div_hw_data(_hw) container_of(_hw, struct div_hw_data, hw_data) argument
588 #define to_dsi_div_hw_data(_hw) container_of(_hw, struct dsi_div_hw_data, hw) argument
707 #define to_pll5_mux_hw_data(_hw) container_of(_hw, struct pll5_mux_hw_data, hw) argument
797 #define to_sipll5(_hw) container_of(_hw, struct sipll5, hw) argument
965 #define to_pll(_hw) container_of(_hw, struct pll_clk, hw) argument
1229 #define to_mod_clock(_hw) container_of(_hw, struct mod_clock, hw) argument
/drivers/clk/mxs/
A Dclk-pll.c30 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw) argument

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