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Searched refs:_i (Results 1 – 25 of 49) sorted by relevance

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/drivers/net/ethernet/intel/i40e/
A Di40e_register.h74 #define I40E_PRTDCB_RETSTCC(_i) (0x00122180 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ argument
109 #define I40E_PRTDCB_RUPTQ(_i) (0x00122400 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ argument
116 #define I40E_PRTDCB_TCMSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ argument
127 #define I40E_PRTDCB_TCWSTC(_i) (0x000A2040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ argument
182 #define I40E_GLGEN_GPIO_CTL(_i) (0x00088100 + ((_i) * 4)) /* _i=0...29 */ /* Reset: POR */ argument
203 #define I40E_GLGEN_MSCA(_i) (0x0008818C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ argument
208 #define I40E_GLGEN_MSCA_OPCODE_MASK(_i) I40E_MASK(_i, I40E_GLGEN_MSCA_OPCODE_SHIFT) argument
210 #define I40E_GLGEN_MSCA_STCODE_MASK(_i) I40E_MASK(_i, I40E_GLGEN_MSCA_STCODE_SHIFT) argument
215 #define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ argument
387 #define I40E_PFINT_ITR0(_i) (0x00038000 + ((_i) * 128)) /* _i=0...2 */ /* Reset: PFR */ argument
[all …]
/drivers/infiniband/hw/irdma/
A Di40iw_hw.h34 #define I40E_GLHMC_VFPDINV(_i) (0x000C8300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ argument
38 #define I40E_GLPES_PFIP4RXDISCARD(_i) (0x00010600 + ((_i) * 4)) /* _i=0...15 */ /* Reset… argument
39 #define I40E_GLPES_PFIP4RXTRUNC(_i) (0x00010700 + ((_i) * 4)) /* _i=0...15 */ /* Reset… argument
40 #define I40E_GLPES_PFIP4TXNOROUTE(_i) (0x00012E00 + ((_i) * 4)) /* _i=0...15 */ /* Reset… argument
41 #define I40E_GLPES_PFIP6RXDISCARD(_i) (0x00011200 + ((_i) * 4)) /* _i=0...15 */ /* Reset… argument
42 #define I40E_GLPES_PFIP6RXTRUNC(_i) (0x00011300 + ((_i) * 4)) /* _i=0...15 */ /* Reset… argument
44 #define I40E_GLPES_PFRDMAVBNDLO(_i) (0x00014800 + ((_i) * 8)) /* _i=0...15 */ /* Reset… argument
45 #define I40E_GLPES_PFIP4TXMCOCTSLO(_i) (0x00012000 + ((_i) * 8)) /* _i=0...15 */ /* Reset… argument
46 #define I40E_GLPES_PFIP6RXMCOCTSLO(_i) (0x00011600 + ((_i) * 8)) /* _i=0...15 */ /* Reset… argument
47 #define I40E_GLPES_PFIP6TXMCOCTSLO(_i) (0x00012A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset… argument
[all …]
A Dicrdma_hw.h19 #define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4)) /* _i=0...63 */ argument
40 #define GLHMC_VFPDINV(_i) (0x00528300 + ((_i) * 4)) /* _i=0...31 */ argument
/drivers/net/ethernet/intel/ice/
A Dice_hw_autogen.h9 #define GLCOMM_QUANTA_PROF(_i) (0x002D2D68 + ((_i) * 4)) argument
478 #define GLPRT_RFC(_i) (0x00380AC0 + ((_i) * 8)) argument
479 #define GLPRT_RJC(_i) (0x00380B00 + ((_i) * 8)) argument
481 #define GLPRT_ROC(_i) (0x00380240 + ((_i) * 8)) argument
482 #define GLPRT_RUC(_i) (0x00380200 + ((_i) * 8)) argument
488 #define GLV_BPRCL(_i) (0x003B6000 + ((_i) * 8)) argument
489 #define GLV_BPTCL(_i) (0x0030E000 + ((_i) * 8)) argument
490 #define GLV_GORCL(_i) (0x003B0000 + ((_i) * 8)) argument
491 #define GLV_GOTCL(_i) (0x00300000 + ((_i) * 8)) argument
492 #define GLV_MPRCL(_i) (0x003B4000 + ((_i) * 8)) argument
[all …]
/drivers/net/ethernet/intel/ixgbe/
A Dixgbe_type.h280 #define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \ argument
309 #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \ argument
311 #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \ argument
313 #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \ argument
315 #define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \ argument
317 #define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \ argument
319 #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \ argument
333 #define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \ argument
359 #define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ argument
361 #define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ argument
[all …]
/drivers/net/dsa/qca/
A Dqca8k.h103 #define QCA8K_LED_CTRL_REG(_i) (0x050 + (_i) * 4) argument
108 #define QCA8K_LED_CTRL_SHIFT(_i) (((_i) % 2) * 16) argument
137 #define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) argument
151 #define QCA8K_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4)) argument
176 #define QCA8K_REG_EEE_CTRL_LPI_EN(_i) ((_i + 1) * 2) argument
187 #define QCA8K_REG_PORT_VLAN_CTRL0(_i) (0x420 + (_i * 8)) argument
192 #define QCA8K_REG_PORT_VLAN_CTRL1(_i) (0x424 + (_i * 8)) argument
252 #define QCA8K_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc) argument
275 #define QCA8K_REG_GOL_TRUNK_SHIFT(_i) ((_i) * 8) argument
285 #define QCA8K_REG_GOL_TRUNK_ID_SHIFT(_i) (((_i) / 2) * 16) argument
[all …]
/drivers/input/mouse/
A Dalps.h92 #define SS4_MF_LF_V2(_b, _i) ((_b[1 + (_i) * 3] & 0x0004) == 0x0004) argument
96 #define SS4_STD_MF_X_V2(_b, _i) (((_b[0 + (_i) * 3] << 5) & 0x00E0) | \ argument
97 ((_b[1 + _i * 3] << 5) & 0x1F00) \
100 #define SS4_PLUS_STD_MF_X_V2(_b, _i) (((_b[0 + (_i) * 3] << 4) & 0x0070) | \ argument
104 #define SS4_STD_MF_Y_V2(_b, _i) (((_b[1 + (_i) * 3] << 3) & 0x0010) | \ argument
106 ((_b[2 + (_i) * 3] << 4) & 0x0E00) \
109 #define SS4_BTL_MF_X_V2(_b, _i) (SS4_STD_MF_X_V2(_b, _i) | \ argument
110 ((_b[0 + (_i) * 3] >> 3) & 0x0010) \
113 #define SS4_PLUS_BTL_MF_X_V2(_b, _i) (SS4_PLUS_STD_MF_X_V2(_b, _i) | \ argument
117 #define SS4_BTL_MF_Y_V2(_b, _i) (SS4_STD_MF_Y_V2(_b, _i) | \ argument
[all …]
/drivers/net/ethernet/wangxun/libwx/
A Dwx_type.h33 #define WX_MIS_RST_LAN_RST(_i) BIT((_i) + 1) argument
84 #define WX_RDM_VF_RE(_i) (0x12004 + ((_i) * 4)) argument
85 #define WX_RDM_PF_QDE(_i) (0x12080 + ((_i) * 4)) argument
86 #define WX_RDM_VFRE_CLR(_i) (0x120A0 + ((_i) * 4)) argument
99 #define WX_CFG_TAG_TPID(_i) (0x14430 + ((_i) * 4)) argument
128 #define WX_TDM_VF_TE(_i) (0x18004 + ((_i) * 4)) argument
398 #define WX_PX_IC(_i) (0x120 + (_i) * 4) argument
399 #define WX_PX_IMS(_i) (0x140 + (_i) * 4) argument
400 #define WX_PX_IMC(_i) (0x150 + (_i) * 4) argument
405 #define WX_PX_ITR(_i) (0x200 + (_i) * 4) argument
[all …]
/drivers/crypto/cavium/nitrox/
A Dnitrox_csr.h21 #define EMU_BIST_STATUSX(_i) (0x1402700 + ((_i) * 0x40000)) argument
29 #define EFL_CORE_BIST_REGX(_i) (0x1240100 + ((_i) * 0x400)) argument
33 #define PEM_BIST_STATUSX(_i) (0x1080468 | ((_i) << 18)) argument
36 #define EMU_SE_ENABLEX(_i) (0x1400000 + ((_i) * 0x40000)) argument
37 #define EMU_AE_ENABLEX(_i) (0x1400008 + ((_i) * 0x40000)) argument
38 #define EMU_WD_INT_ENA_W1SX(_i) (0x1402318 + ((_i) * 0x40000)) argument
39 #define EMU_GE_INT_ENA_W1SX(_i) (0x1402518 + ((_i) * 0x40000)) argument
40 #define EMU_FUSE_MAPX(_i) (0x1402708 + ((_i) * 0x40000)) argument
47 #define UCD_SE_CNTX(_i) (0x12C0040 + ((_i) * 0x1000)) argument
48 #define UCD_AE_CNTX(_i) (0x12C0048 + ((_i) * 0x800)) argument
[all …]
/drivers/net/ethernet/intel/igb/
A De1000_regs.h286 #define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4)) argument
287 #define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ argument
289 #define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ argument
292 #define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8)) argument
293 #define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4)) argument
294 #define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4)) argument
295 #define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8)) argument
296 #define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8)) argument
297 #define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8)) argument
323 #define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) argument
[all …]
/drivers/net/wireless/ath/ath9k/
A Dreg_wow.h127 #define AR_WOW_LEN1_SHIFT(_i) ((0x3 - ((_i) & 0x3)) << 0x3) argument
128 #define AR_WOW_LENGTH1_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN1_SHIFT(_i)) argument
129 #define AR_WOW_LEN2_SHIFT(_i) ((0x7 - ((_i) & 0x7)) << 0x3) argument
130 #define AR_WOW_LENGTH2_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN2_SHIFT(_i)) argument
131 #define AR_WOW_LEN3_SHIFT(_i) ((0xb - ((_i) & 0xb)) << 0x3) argument
132 #define AR_WOW_LENGTH3_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN3_SHIFT(_i)) argument
133 #define AR_WOW_LEN4_SHIFT(_i) ((0xf - ((_i) & 0xf)) << 0x3) argument
134 #define AR_WOW_LENGTH4_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN4_SHIFT(_i)) argument
A Dar9003_phy.h981 #define AR_PHY_TX_IQCAL_CORR_COEFF_B1(_i) (AR_SM1_BASE + 0x450 + ((_i) << 2)) argument
1038 #define AR_PHY_TX_IQCAL_CORR_COEFF_B2(_i) (AR_SM2_BASE + 0x450 + ((_i) << 2)) argument
1057 #define AR_PHY_SWITCH_CHAIN(_i) (AR_PHY_SWITCH_CHAIN_0 + (AR_PHY_CHAIN_OFFSET * (_i))) argument
1058 #define AR_PHY_EXT_ATTEN_CTL(_i) (AR_PHY_EXT_ATTEN_CTL_0 + (AR_PHY_CHAIN_OFFSET * (_i))) argument
1060 #define AR_PHY_RXGAIN(_i) (AR_PHY_FORCEMAX_GAINS_0 + (AR_PHY_CHAIN_OFFSET * (_i))) argument
1061 #define AR_PHY_TPCRG5(_i) (AR_PHY_TPC_5_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) argument
1062 #define AR_PHY_PDADC_TAB(_i) (AR_PHY_PDADC_TAB_0 + (AR_PHY_CHAIN_OFFSET * (_i))) argument
1064 #define AR_PHY_CAL_MEAS_0(_i) (AR_PHY_IQ_ADC_MEAS_0_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) argument
1065 #define AR_PHY_CAL_MEAS_1(_i) (AR_PHY_IQ_ADC_MEAS_1_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) argument
1066 #define AR_PHY_CAL_MEAS_2(_i) (AR_PHY_IQ_ADC_MEAS_2_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) argument
[all …]
A Dar9002_phy.h190 #define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12)) argument
305 #define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12)) argument
385 #define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12)) argument
386 #define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12)) argument
387 #define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12)) argument
388 #define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12)) argument
A Dreg.h390 #define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2)) argument
411 #define AR_QCBRCFG(_i) (AR_Q0_CBRCFG + ((_i)<<2)) argument
450 #define AR_QMISC(_i) (AR_Q0_MISC + ((_i)<<2)) argument
478 #define AR_QSTS(_i) (AR_Q0_STS + ((_i)<<2)) argument
514 #define AR_DQCUMASK(_i) (AR_D0_QCUMASK + ((_i)<<2)) argument
528 #define AR_DLCL_IFS(_i) (AR_D0_LCL_IFS + ((_i)<<2)) argument
548 #define AR_DRETRY_LIMIT(_i) (AR_D0_RETRY_LIMIT + ((_i)<<2)) argument
567 #define AR_DCHNTIME(_i) (AR_D0_CHNTIME + ((_i)<<2)) argument
583 #define AR_DMISC(_i) (AR_D0_MISC + ((_i)<<2)) argument
1905 #define AR_MCI_COEX_WL_WEIGHTS(_i) (0x18b0 + (_i << 2)) argument
[all …]
/drivers/net/ethernet/intel/e1000e/
A Dregs.h108 #define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ argument
109 (0x054E0 + ((_i - 16) * 8)))
110 #define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ argument
111 (0x054E4 + ((_i - 16) * 8)))
112 #define E1000_SHRAL(_i) (0x05438 + ((_i) * 8)) argument
113 #define E1000_SHRAH(_i) (0x0543C + ((_i) * 8)) argument
224 #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */ argument
225 #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */ argument
A Dich8lan.h47 #define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8)) argument
48 #define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8)) argument
125 #define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) argument
126 #define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) argument
127 #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) argument
128 #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) argument
129 #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) argument
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/
A Ddml2_debug.h33 for (int _i = 0; _i < (int) size; _i++) { \
34 DML_LOG_INTERNAL(format(field[_i])); \
35 if (_i + 1 == (int) size) \
42 for (int _i = 0; _i < (int) size0; _i++) { \
45 DML_LOG_INTERNAL(format(field[_i][_j])); \
51 if (_i + 1 == (int) size0) \
59 for (int _i = 0; _i < (int) size0; _i++) { \
64 DML_LOG_INTERNAL(format(field[_i][_j][_k])); \
75 if (_i + 1 == (int) size0) \
/drivers/gpu/drm/armada/
A Darmada_crtc.h18 #define armada_reg_queue_mod(_r, _i, _v, _m, _o) \ argument
21 __reg[_i].offset = _o; \
22 __reg[_i].mask = ~(_m); \
23 __reg[_i].val = _v; \
24 _i++; \
27 #define armada_reg_queue_set(_r, _i, _v, _o) \ argument
28 armada_reg_queue_mod(_r, _i, _v, ~0, _o)
30 #define armada_reg_queue_end(_r, _i) \ argument
31 armada_reg_queue_mod(_r, _i, 0, 0, ~0)
/drivers/net/ethernet/intel/iavf/
A Diavf_register.h58 #define IAVF_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=… argument
61 #define IAVF_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */ argument
62 #define IAVF_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */ argument
64 #define IAVF_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ argument
/drivers/net/ethernet/intel/igc/
A Digc_regs.h93 #define IGC_RETA(_i) (0x05C00 + ((_i) * 4)) argument
95 #define IGC_RSSRK(_i) (0x05C80 + ((_i) * 4)) argument
100 #define IGC_PSRTYPE(_i) (0x05480 + ((_i) * 4)) argument
220 #define IGC_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */ argument
221 #define IGC_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate INTR Ext*/ argument
322 #define IGC_WUPM_REG(_i) (0x05A00 + ((_i) * 4)) argument
/drivers/net/ethernet/intel/igbvf/
A Dregs.h55 #define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ argument
56 (0x054E0 + ((_i - 16) * 8)))
57 #define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ argument
58 (0x054E4 + ((_i - 16) * 8)))
/drivers/net/wireless/ath/carl9170/
A Dphy.h185 #define AR9170_PHY_REG_TIMING_CTRL4(_i) (AR9170_PHY_REG_BASE + \ argument
186 (0x0120 + ((_i) << 12)))
309 0x01b4 + ((_i) << 12))
381 #define AR9170_PHY_REG_CAL_MEAS_0(_i) (AR9170_PHY_REG_BASE + \ argument
382 0x0410 + ((_i) << 12))
383 #define AR9170_PHY_REG_CAL_MEAS_1(_i) (AR9170_PHY_REG_BASE + \ argument
384 0x0414 \ + ((_i) << 12))
385 #define AR9170_PHY_REG_CAL_MEAS_2(_i) (AR9170_PHY_REG_BASE + \ argument
386 0x0418 + ((_i) << 12))
387 #define AR9170_PHY_REG_CAL_MEAS_3(_i) (AR9170_PHY_REG_BASE + \ argument
[all …]
/drivers/clk/at91/
A Dpmc.h127 u8 _i; \
128 for (_i = 0; _i < (_count); _i++) \
129 (_table)[_i] = _i; \
134 u8 _i; \
135 for (_i = 0; _i < (_count); _i++) { \
136 (_to)[_i] = (_from)[_i]; \
/drivers/net/ethernet/intel/idpf/
A Didpf_lan_vf_regs.h122 #define VF_QF_HENA(_i) (0x0000C400 + ((_i) * 4)) argument
124 #define VF_QF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) argument
126 #define VF_QF_HLUT(_i) (0x0000D000 + ((_i) * 4)) argument
/drivers/net/ethernet/wangxun/txgbe/
A Dtxgbe_type.h56 #define TXGBE_MIS_RST_MAC_RST(_i) BIT(20 - (_i) * 3) argument
58 #define TXGBE_MIS_PRB_CTL_LAN_UP(_i) BIT(1 - (_i)) argument
63 #define TXGBE_SPI_ILDR_STATUS_LAN_SW_RST(_i) BIT((_i) + 9) /* lan soft reset done */ argument
123 #define TXGBE_RDB_FDIR_IP6(_i) (0x1950C + ((_i) * 4)) /* 0-2 */ argument
157 #define TXGBE_RDB_FDIR_FLEX_CFG(_i) (0x19580 + ((_i) * 4)) argument

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