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/drivers/clk/renesas/
A Drzg2l-cpg.h148 #define DEF_TYPE(_name, _id, _type...) \ argument
149 { .name = _name, .id = _id, .type = _type }
151 DEF_TYPE(_name, _id, _type, .parent = _parent)
152 #define DEF_SAMPLL(_name, _id, _parent, _conf) \ argument
157 #define DEF_INPUT(_name, _id) \ argument
158 DEF_TYPE(_name, _id, CLK_TYPE_IN)
224 .id = MOD_CLK_BASE + (_id), \
251 #define DEF_RST_MON(_id, _off, _bit, _monbit) \ argument
252 [_id] = { \
257 #define DEF_RST(_id, _off, _bit) \ argument
[all …]
A Drcar-gen3-cpg.h37 #define DEF_GEN3_SDH(_name, _id, _parent, _offset) \ argument
40 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
44 DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
50 DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
53 #define DEF_GEN3_OSC(_name, _id, _parent, _div) \ argument
54 DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
57 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
63 #define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1) \ argument
64 DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \
66 #define DEF_FIXED_RPCSRC_D3(_name, _id, _parent0, _parent1) \ argument
[all …]
A Drcar-gen4-cpg.h35 #define DEF_GEN4_SDH(_name, _id, _parent, _offset) \ argument
38 #define DEF_GEN4_SD(_name, _id, _parent, _offset) \ argument
39 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
42 DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL, \
46 #define DEF_GEN4_OSC(_name, _id, _parent, _div) \ argument
47 DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div)
49 #define DEF_GEN4_PLL_F8_25(_name, _idx, _id, _parent) \ argument
52 #define DEF_GEN4_PLL_V8_25(_name, _idx, _id, _parent) \ argument
55 #define DEF_GEN4_PLL_F9_24(_name, _idx, _id, _parent) \ argument
58 #define DEF_GEN4_PLL_V9_24(_name, _idx, _id, _parent) \ argument
[all …]
A Drenesas-cpg-mssr.h71 #define DEF_TYPE(_name, _id, _type...) \ argument
72 { .name = _name, .id = _id, .type = _type }
73 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
74 DEF_TYPE(_name, _id, _type, .parent = _parent)
76 #define DEF_INPUT(_name, _id) \ argument
77 DEF_TYPE(_name, _id, CLK_TYPE_IN)
78 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ argument
80 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
82 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument
84 #define DEF_RATE(_name, _id, _rate) \ argument
[all …]
A Drzv2h-cpg.h193 #define DEF_TYPE(_name, _id, _type...) \ argument
194 { .name = _name, .id = _id, .type = _type }
195 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
196 DEF_TYPE(_name, _id, _type, .parent = _parent)
197 #define DEF_PLL(_name, _id, _parent, _pll_packed) \ argument
199 #define DEF_INPUT(_name, _id) \ argument
200 DEF_TYPE(_name, _id, CLK_TYPE_IN)
201 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ argument
207 DEF_TYPE(_name, _id, CLK_TYPE_DDIV, \
213 DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable)
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/drivers/clk/samsung/
A Dclk.h45 #define ALIAS(_id, dname, a) \ argument
47 .id = _id, \
72 .id = _id, \
99 .id = _id, \
133 .id = _id, \
152 __MUX(_id, cname, pnames, o, s, w, 0, 0)
183 .id = _id, \
225 .id = _id, \
235 __GATE(_id, cname, pname, o, b, f, gf)
273 .id = _id, \
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/drivers/clk/mediatek/
A Dclk-mtk.h37 #define GATE_DUMMY(_id, _name) { \ argument
38 .id = _id, \
51 #define FIXED_CLK(_id, _name, _parent, _rate) { \ argument
52 .id = _id, \
73 .id = _id, \
81 #define FACTOR(_id, _name, _parent, _mult, _div) \ argument
114 .id = _id, \
146 MUX_FLAGS(_id, _name, _parents, _reg, \
150 .id = _id, \
164 .id = _id, \
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A Dclk-mt8188-infra_ao.c46 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
49 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ argument
50 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
53 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
56 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ argument
57 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
59 #define GATE_INFRA_AO2(_id, _name, _parent, _shift) \ argument
70 #define GATE_INFRA_AO3(_id, _name, _parent, _shift) \ argument
71 GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0)
77 #define GATE_INFRA_AO4(_id, _name, _parent, _shift) \ argument
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A Dclk-mt8195-infra_ao.c45 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
48 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ argument
49 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
55 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ argument
56 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
62 #define GATE_INFRA_AO2(_id, _name, _parent, _shift) \ argument
63 GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, 0)
69 #define GATE_INFRA_AO3(_id, _name, _parent, _shift) \ argument
70 GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0)
76 #define GATE_INFRA_AO4(_id, _name, _parent, _shift) \ argument
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A Dclk-mux.h41 #define __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx, \ argument
45 .id = _id, \
62 #define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ argument
65 __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
73 __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
84 GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
92 GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, \
100 MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
108 MUX_GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, \
113 #define MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \ argument
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A Dclk-mt8188-vdo1.c52 #define GATE_VDO1_0(_id, _name, _parent, _shift) \ argument
53 GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
55 #define GATE_VDO1_1(_id, _name, _parent, _shift) \ argument
56 GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
58 #define GATE_VDO1_2(_id, _name, _parent, _shift) \ argument
59 GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
61 #define GATE_VDO1_3(_id, _name, _parent, _shift) \ argument
64 #define GATE_VDO1_3_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
65 GATE_MTK_FLAGS(_id, _name, _parent, &vdo1_3_cg_regs, _shift, \
68 #define GATE_VDO1_4(_id, _name, _parent, _shift) \ argument
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A Dclk-mt8186-infra_ao.c38 #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
39 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
42 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ argument
43 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
45 #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
49 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ argument
50 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
56 #define GATE_INFRA_AO2(_id, _name, _parent, _shift) \ argument
57 GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, 0)
63 #define GATE_INFRA_AO3(_id, _name, _parent, _shift) \ argument
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A Dclk-mt7988-infracfg.c128 #define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
129 GATE_MTK_FLAGS(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
132 #define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
133 GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
136 #define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
137 GATE_MTK_FLAGS(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
141 GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
144 #define GATE_INFRA0(_id, _name, _parent, _shift) GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0) argument
146 #define GATE_INFRA1(_id, _name, _parent, _shift) GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0) argument
148 #define GATE_INFRA2(_id, _name, _parent, _shift) GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0) argument
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A Dclk-mt8195-vdo1.c43 #define GATE_VDO1_0(_id, _name, _parent, _shift) \ argument
44 GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
46 #define GATE_VDO1_1(_id, _name, _parent, _shift) \ argument
47 GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
49 #define GATE_VDO1_2(_id, _name, _parent, _shift) \ argument
50 GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
52 #define GATE_VDO1_2_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
53 GATE_MTK_FLAGS(_id, _name, _parent, &vdo1_2_cg_regs, _shift, \
56 #define GATE_VDO1_3(_id, _name, _parent, _shift) \ argument
57 GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
[all …]
A Dclk-mt8183-ipu_conn.c44 #define GATE_IPU_CONN(_id, _name, _parent, _shift) \ argument
45 GATE_MTK(_id, _name, _parent, &ipu_conn_cg_regs, _shift, \
48 #define GATE_IPU_CONN_APB(_id, _name, _parent, _shift) \ argument
49 GATE_MTK(_id, _name, _parent, &ipu_conn_apb_cg_regs, _shift, \
52 #define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift) \ argument
53 GATE_MTK(_id, _name, _parent, &ipu_conn_axi_cg_regs, _shift, \
56 #define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift) \ argument
57 GATE_MTK(_id, _name, _parent, &ipu_conn_axi1_cg_regs, _shift, \
60 #define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift) \ argument
61 GATE_MTK(_id, _name, _parent, &ipu_conn_axi2_cg_regs, _shift, \
A Dclk-mt8186-vdec.c39 #define GATE_VDEC0(_id, _name, _parent, _shift) \ argument
40 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
42 #define GATE_VDEC1(_id, _name, _parent, _shift) \ argument
43 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
45 #define GATE_VDEC2(_id, _name, _parent, _shift) \ argument
46 GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
48 #define GATE_VDEC3(_id, _name, _parent, _shift) \ argument
49 GATE_MTK(_id, _name, _parent, &vdec3_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
A Dclk-mt8167.c658 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
659 .id = _id, \
724 #define GATE_TOP0(_id, _name, _parent, _shift) \ argument
725 GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
727 #define GATE_TOP0_I(_id, _name, _parent, _shift) \ argument
730 #define GATE_TOP1(_id, _name, _parent, _shift) \ argument
733 #define GATE_TOP2(_id, _name, _parent, _shift) \ argument
736 #define GATE_TOP2_I(_id, _name, _parent, _shift) \ argument
739 #define GATE_TOP3(_id, _name, _parent, _shift) \ argument
742 #define GATE_TOP4_I(_id, _name, _parent, _shift) \ argument
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/drivers/regulator/
A Dmax77541-regulator.c55 #define MAX77540_BUCK(_id, _ops) \ argument
56 { .id = MAX77541_BUCK ## _id, \
57 .name = "buck"#_id, \
58 .of_match = "buck"#_id, \
61 .enable_mask = MAX77541_BIT_M ## _id ## _EN, \
66 .vsel_reg = MAX77541_REG_M ## _id ## _VOUT, \
74 #define MAX77541_BUCK(_id, _ops) \ argument
75 { .id = MAX77541_BUCK ## _id, \
76 .name = "buck"#_id, \
77 .of_match = "buck"#_id, \
[all …]
A Dmax77826-regulator.c118 #define MAX77826_LDO(_id, _type) \ argument
119 [MAX77826_LDO ## _id] = { \
120 .id = MAX77826_LDO ## _id, \
121 .name = "LDO"#_id, \
122 .of_match = of_match_ptr("LDO"#_id), \
135 #define MAX77826_BUCK(_idx, _id, _ops) \ argument
136 [MAX77826_ ## _id] = { \
137 .id = MAX77826_ ## _id, \
138 .name = #_id, \
139 .of_match = of_match_ptr(#_id), \
[all …]
A Drtq2134-regulator.c26 #define RTQ2134_REG_FLT_RECORDBUCK(_id) (0x14 + (_id)) argument
27 #define RTQ2134_REG_FLT_BUCKCTRL(_id) (0x37 + (_id)) argument
270 #define RTQ2134_BUCK_DESC(_id) { \ argument
272 .name = "rtq2134_buck" #_id, \
273 .of_match = of_match_ptr("buck" #_id), \
275 .id = RTQ2134_IDX_BUCK##_id, \
282 .vsel_reg = RTQ2134_REG_BUCK##_id##_DVS0CFG1, \
284 .enable_reg = RTQ2134_REG_BUCK##_id##_DVS0CFG0, \
289 .ramp_reg = RTQ2134_REG_BUCK##_id##_RSPCFG, \
296 .mode_reg = RTQ2134_REG_BUCK##_id##_DVS0CFG0, \
[all …]
A Dhi6421-regulator.c131 [HI6421_##_id] = { \
133 .name = #_id, \
138 .id = HI6421_##_id, \
170 [HI6421_##_id] = { \
172 .name = #_id, \
210 [HI6421_##_id] = { \
212 .name = #_id, \
247 [HI6421_##_id] = { \
249 .name = #_id, \
284 [HI6421_##_id] = { \
[all …]
A Dmpq7920.c26 #define MPQ7920BUCK(_name, _id, _ilim) \ argument
27 [MPQ7920_BUCK ## _id] = { \
28 .id = MPQ7920_BUCK ## _id, \
39 .csel_reg = MPQ7920_BUCK ##_id## _REG_C, \
43 MPQ7920_BUCK ## _id), \
44 .vsel_reg = MPQ7920_BUCK ##_id## _REG_A, \
49 .soft_start_reg = MPQ7920_BUCK ##_id## _REG_C, \
55 [MPQ7920_LDO ## _id] = { \
56 .id = MPQ7920_LDO ## _id, \
64 .vsel_reg = MPQ7920_LDO ##_id## _REG_A, \
[all …]
/drivers/clk/pistachio/
A Dclk.h19 #define GATE(_id, _name, _pname, _reg, _shift) \ argument
21 .id = _id, \
39 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument
41 .id = _id, \
59 #define DIV(_id, _name, _pname, _reg, _width) \ argument
61 .id = _id, \
71 .id = _id, \
86 #define FIXED_FACTOR(_id, _name, _pname, _div) \ argument
88 .id = _id, \
121 .id = _id, \
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/drivers/clk/rockchip/
A Dclk.h709 .id = _id, \
730 .id = _id, \
752 .id = _id, \
770 .id = _id, \
789 .id = _id, \
807 .id = _id, \
826 .id = _id, \
845 .id = _id, \
862 .id = _id, \
880 .id = _id, \
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/drivers/clk/x86/
A Dclk-cgu.h117 #define LGM_PLL(_id, _name, _pdata, _flags, \ argument
120 .id = _id, \
150 .id = _id, \
203 #define LGM_MUX(_id, _name, _pdata, _f, _reg, \ argument
206 .id = _id, \
222 .id = _id, \
241 #define LGM_GATE(_id, _name, _pname, _f, _reg, \ argument
244 .id = _id, \
259 #define LGM_FIXED(_id, _name, _pname, _f, _reg, \ argument
262 .id = _id, \
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