Home
last modified time | relevance | path

Searched refs:_name (Results 1 – 25 of 647) sorted by relevance

12345678910>>...26

/drivers/clk/spacemit/
A Dccu_mix.h53 #define CCU_PARENT_NAME(_name) { .fw_name = #_name } argument
58 .name = #_name, \
69 static struct ccu_mix _name = { \
78 static struct ccu_mix _name = { \
86 static struct ccu_mix _name = { \
96 static struct ccu_mix _name = { \
106 static struct ccu_mix _name = { \
122 static struct ccu_mix _name = { \
134 static struct ccu_mix _name = { \
146 static struct ccu_mix _name = { \
[all …]
/drivers/thermal/qcom/
A Dtsens.h123 [_name##_##1] = REG_FIELD(_offset, 1, 1), \
124 [_name##_##2] = REG_FIELD(_offset, 2, 2), \
125 [_name##_##3] = REG_FIELD(_offset, 3, 3), \
126 [_name##_##4] = REG_FIELD(_offset, 4, 4), \
127 [_name##_##5] = REG_FIELD(_offset, 5, 5), \
128 [_name##_##6] = REG_FIELD(_offset, 6, 6), \
129 [_name##_##7] = REG_FIELD(_offset, 7, 7), \
130 [_name##_##8] = REG_FIELD(_offset, 8, 8), \
131 [_name##_##9] = REG_FIELD(_offset, 9, 9), \
137 [_name##_##15] = REG_FIELD(_offset, 15, 15)
[all …]
/drivers/staging/rtl8723bs/hal/
A Dodm_interface.h16 #define _reg_all(_name) ODM_##_name argument
17 #define _reg_ic(_name, _ic) ODM_##_name##_ic argument
18 #define _bit_all(_name) BIT_##_name argument
19 #define _bit_ic(_name, _ic) BIT_##_name##_ic argument
29 #define _reg_11N(_name) ODM_REG_##_name##_11N argument
30 #define _bit_11N(_name) ODM_BIT_##_name##_11N argument
32 #define _cat(_name, _ic_type, _func) _func##_11N(_name) argument
37 #define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg) argument
38 #define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit) argument
/drivers/clk/sprd/
A Dgate.h42 .hw.init = _fn(_name, _parent, \
50 SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
56 SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \
66 #define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \ argument
68 SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, 0, \
75 SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \
85 SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
97 #define SPRD_SC_GATE_CLK_HW(_struct, _name, _parent, _reg, \ argument
100 SPRD_SC_GATE_CLK_HW_OPS(_struct, _name, _parent, _reg, \
104 #define SPRD_GATE_CLK_HW(_struct, _name, _parent, _reg, \ argument
[all …]
A Dcomposite.h30 .hw.init = _fn(_name, _parent, \
35 #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \ argument
37 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
41 #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \ argument
43 SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, NULL, \
49 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
54 #define SPRD_COMP_CLK_DATA(_struct, _name, _parent, _reg, _mshift, \ argument
56 SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, NULL, \
64 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
69 #define SPRD_COMP_CLK_DATA_OFFSET(_struct, _name, _parent, _reg, \ argument
[all …]
/drivers/clk/renesas/
A Drzg2l-cpg.h148 #define DEF_TYPE(_name, _id, _type...) \ argument
149 { .name = _name, .id = _id, .type = _type }
150 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
151 DEF_TYPE(_name, _id, _type, .parent = _parent)
152 #define DEF_SAMPLL(_name, _id, _parent, _conf) \ argument
157 #define DEF_INPUT(_name, _id) \ argument
158 DEF_TYPE(_name, _id, CLK_TYPE_IN)
176 #define DEF_MUX(_name, _id, _conf, _parent_names) \ argument
191 #define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \ argument
197 #define DEF_DSI_DIV(_name, _id, _parent, _flag) \ argument
[all …]
A Drcar-gen3-cpg.h37 #define DEF_GEN3_SDH(_name, _id, _parent, _offset) \ argument
40 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
44 DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
50 DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
53 #define DEF_GEN3_OSC(_name, _id, _parent, _div) \ argument
54 DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
57 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
63 #define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1) \ argument
64 DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \
66 #define DEF_FIXED_RPCSRC_D3(_name, _id, _parent0, _parent1) \ argument
[all …]
A Drcar-gen4-cpg.h35 #define DEF_GEN4_SDH(_name, _id, _parent, _offset) \ argument
38 #define DEF_GEN4_SD(_name, _id, _parent, _offset) \ argument
39 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
42 DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL, \
46 #define DEF_GEN4_OSC(_name, _id, _parent, _div) \ argument
47 DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div)
49 #define DEF_GEN4_PLL_F8_25(_name, _idx, _id, _parent) \ argument
52 #define DEF_GEN4_PLL_V8_25(_name, _idx, _id, _parent) \ argument
55 #define DEF_GEN4_PLL_F9_24(_name, _idx, _id, _parent) \ argument
58 #define DEF_GEN4_PLL_V9_24(_name, _idx, _id, _parent) \ argument
[all …]
A Drzv2h-cpg.h193 #define DEF_TYPE(_name, _id, _type...) \ argument
194 { .name = _name, .id = _id, .type = _type }
195 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
196 DEF_TYPE(_name, _id, _type, .parent = _parent)
197 #define DEF_PLL(_name, _id, _parent, _pll_packed) \ argument
199 #define DEF_INPUT(_name, _id) \ argument
200 DEF_TYPE(_name, _id, CLK_TYPE_IN)
201 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ argument
207 DEF_TYPE(_name, _id, CLK_TYPE_DDIV, \
215 DEF_TYPE(_name, _id, CLK_TYPE_SMUX, \
[all …]
A Drenesas-cpg-mssr.h71 #define DEF_TYPE(_name, _id, _type...) \ argument
72 { .name = _name, .id = _id, .type = _type }
73 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
74 DEF_TYPE(_name, _id, _type, .parent = _parent)
76 #define DEF_INPUT(_name, _id) \ argument
77 DEF_TYPE(_name, _id, CLK_TYPE_IN)
80 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
84 #define DEF_RATE(_name, _id, _rate) \ argument
85 DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
102 #define DEF_MOD(_name, _mod, _parent...) \ argument
[all …]
/drivers/clk/sophgo/
A Dclk-cv18xx-ip.h70 struct cv1800_clk_gate _name = { \
108 struct cv1800_clk_div _name = \
116 struct cv1800_clk_bypass_div _name = { \
117 .div = _CV1800_DIV(_name, _parent, \
128 struct cv1800_clk_div _name = \
129 _CV1800_FIXED_DIV(_name, _parent, \
167 struct cv1800_clk_mux _name = \
179 .mux = _CV1800_MUX(_name, _parent, \
199 struct cv1800_clk_mmux _name = { \
226 #define CV1800_ACLK(_name, _parent, \ argument
[all …]
/drivers/clk/sunxi-ng/
A Dccu_div.h96 .hw.init = CLK_HW_INIT(_name, \
119 .hw.init = CLK_HW_INIT_HW(_name, \
139 .hw.init = CLK_HW_INIT_PARENTS(_name, \
158 .hw.init = CLK_HW_INIT_PARENTS(_name, \
169 SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \
188 SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \
203 .hw.init = CLK_HW_INIT(_name, \
212 SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \
225 .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \
250 .hw.init = CLK_HW_INIT_PARENTS_HW(_name, \
[all …]
A Dccu_mp.h48 .hw.init = CLK_HW_INIT_PARENTS(_name, \
70 .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \
89 .hw.init = CLK_HW_INIT_PARENTS(_name, \
96 #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \ argument
101 SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
123 .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \
143 .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \
155 SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(_struct, _name, _parents, \
166 SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(_struct, _name, _parents, \
196 .hw.init = CLK_HW_INIT_PARENTS_HW(_name, \
[all …]
A Dccu_gate.h19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
24 .hw.init = CLK_HW_INIT(_name, \
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
36 .hw.init = CLK_HW_INIT_HW(_name, \
43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
48 .hw.init = CLK_HW_INIT_FW_NAME(_name, \
64 .hw.init = CLK_HW_INIT_HWS(_name, \
71 #define SUNXI_CCU_GATE_HWS_WITH_PREDIV(_struct, _name, _parent, _reg, \ argument
79 .hw.init = CLK_HW_INIT_HWS(_name, \
92 CLK_HW_INIT_PARENTS_DATA(_name, \
[all …]
A Dccu_mux.h57 .hw.init = CLK_HW_INIT_PARENTS(_name, \
68 SUNXI_CCU_MUX_TABLE_WITH_GATE_FEAT(_struct, _name, _parents, \
76 SUNXI_CCU_MUX_TABLE_WITH_GATE_FEAT(_struct, _name, _parents, \
80 #define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \ argument
82 SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, NULL, \
88 SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, NULL, \
98 .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \
105 #define SUNXI_CCU_MUX_DATA(_struct, _name, _parents, _reg, \ argument
107 SUNXI_CCU_MUX_DATA_WITH_GATE(_struct, _name, _parents, _reg, \
110 #define SUNXI_CCU_MUX_HW_WITH_GATE(_struct, _name, _parents, _reg, \ argument
[all …]
/drivers/clk/starfive/
A Dclk-starfive-jh71x0.h34 .name = _name, \
42 .name = _name, \
50 .name = _name, \
56 #define JH71X0_FDIV(_idx, _name, _parent) \ argument
58 .name = _name, \
66 .name = _name, \
74 .name = _name, \
83 .name = _name, \
91 .name = _name, \
98 #define JH71X0__INV(_idx, _name, _parent) \ argument
[all …]
/drivers/regulator/
A Dmc13xxx.h56 [prefix ## _name] = { \
63 .id = prefix ## _name, \
67 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
69 .vsel_shift = prefix ## _vsel_reg ## _ ## _name ## VSEL,\
70 .vsel_mask = prefix ## _vsel_reg ## _ ## _name ## VSEL_M,\
74 [prefix ## _name] = { \
81 .id = prefix ## _name, \
85 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
89 [prefix ## _name] = { \
96 .id = prefix ## _name, \
[all …]
/drivers/clk/mediatek/
A Dclk-mtk.h37 #define GATE_DUMMY(_id, _name) { \ argument
39 .name = _name, \
51 #define FIXED_CLK(_id, _name, _parent, _rate) { \ argument
53 .name = _name, \
74 .name = _name, \
81 #define FACTOR(_id, _name, _parent, _mult, _div) \ argument
115 .name = _name, \
146 MUX_FLAGS(_id, _name, _parents, _reg, \
151 .name = _name, \
166 .name = _name, \
[all …]
A Dclk-mt8188-infra_ao.c46 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
49 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ argument
50 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
53 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
56 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ argument
57 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
59 #define GATE_INFRA_AO2(_id, _name, _parent, _shift) \ argument
70 #define GATE_INFRA_AO3(_id, _name, _parent, _shift) \ argument
71 GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0)
77 #define GATE_INFRA_AO4(_id, _name, _parent, _shift) \ argument
[all …]
A Dclk-mt8195-infra_ao.c45 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
48 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ argument
49 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
55 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ argument
56 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
62 #define GATE_INFRA_AO2(_id, _name, _parent, _shift) \ argument
63 GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, 0)
69 #define GATE_INFRA_AO3(_id, _name, _parent, _shift) \ argument
70 GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0)
76 #define GATE_INFRA_AO4(_id, _name, _parent, _shift) \ argument
[all …]
/drivers/clk/mvebu/
A Darmada-37xx-periph.c139 struct clk_mux mux_##_name = { \
199 #define REF_CLK_FULL(_name) \ argument
200 { .name = #_name, \
204 .mux_hw = &mux_##_name.hw, \
210 { .name = #_name, \
214 .mux_hw = &mux_##_name.hw, \
221 { .name = #_name, \
228 { .name = #_name, \
236 { .name = #_name, \
244 { .name = #_name, \
[all …]
/drivers/clk/pistachio/
A Dclk.h19 #define GATE(_id, _name, _pname, _reg, _shift) \ argument
24 .name = _name, \
39 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument
44 .name = _name, \
59 #define DIV(_id, _name, _pname, _reg, _width) \ argument
65 .name = _name, \
75 .name = _name, \
86 #define FIXED_FACTOR(_id, _name, _pname, _div) \ argument
90 .name = _name, \
126 .name = _name, \
[all …]
/drivers/gpu/drm/amd/pm/inc/
A Damdgpu_pm.h101 #define __AMDGPU_DEVICE_ATTR(_name, _mode, _show, _store, _flags, ...) \ argument
102 { .dev_attr = __ATTR(_name, _mode, _show, _store), \
103 .attr_id = device_attr_id__##_name, \
107 #define AMDGPU_DEVICE_ATTR(_name, _mode, _flags, ...) \ argument
108 __AMDGPU_DEVICE_ATTR(_name, _mode, \
109 amdgpu_get_##_name, amdgpu_set_##_name, \
112 #define AMDGPU_DEVICE_ATTR_RW(_name, _flags, ...) \ argument
113 AMDGPU_DEVICE_ATTR(_name, S_IRUGO | S_IWUSR, \
116 #define AMDGPU_DEVICE_ATTR_RO(_name, _flags, ...) \ argument
117 __AMDGPU_DEVICE_ATTR(_name, S_IRUGO, \
[all …]
/drivers/gpu/drm/i915/gt/
A Dintel_gt_sysfs_pm.c147 #define INTEL_GT_SYSFS_SHOW_MAX(_name) INTEL_GT_SYSFS_SHOW(_name, max) argument
148 #define INTEL_GT_SYSFS_SHOW_MIN(_name) INTEL_GT_SYSFS_SHOW(_name, min) argument
151 static struct kobj_attribute attr_##_name = __ATTR_RW(_name)
154 static struct kobj_attribute attr_##_name = __ATTR_RO(_name)
157 static struct device_attribute dev_attr_##_name = __ATTR(_name, 0644, \
160 INTEL_GT_ATTR_RW(_name)
163 static struct device_attribute dev_attr_##_name = __ATTR(_name, 0444, \
166 INTEL_GT_ATTR_RO(_name)
395 INTEL_GT_RPS_SYSFS_ATTR(_name, 0444, _name##_show, NULL, \
398 INTEL_GT_RPS_SYSFS_ATTR(_name, 0644, _name##_show, _name##_store, \
[all …]
/drivers/platform/x86/intel/uncore-frequency/
A Duncore-frequency-common.c162 #define init_attribute_rw(_name) \ argument
165 data->_name##_kobj_attr.show = show_##_name; \
166 data->_name##_kobj_attr.store = store_##_name; \
167 data->_name##_kobj_attr.attr.name = #_name; \
171 #define init_attribute_ro(_name) \ argument
174 data->_name##_kobj_attr.show = show_##_name; \
175 data->_name##_kobj_attr.store = NULL; \
176 data->_name##_kobj_attr.attr.name = #_name; \
180 #define init_attribute_root_ro(_name) \ argument
183 data->_name##_kobj_attr.show = show_##_name; \
[all …]

Completed in 72 milliseconds

12345678910>>...26