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Searched refs:_offset (Results 1 – 25 of 98) sorted by relevance

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/drivers/thermal/qcom/
A Dtsens.h123 [_name##_##1] = REG_FIELD(_offset, 1, 1), \
124 [_name##_##2] = REG_FIELD(_offset, 2, 2), \
125 [_name##_##3] = REG_FIELD(_offset, 3, 3), \
126 [_name##_##4] = REG_FIELD(_offset, 4, 4), \
127 [_name##_##5] = REG_FIELD(_offset, 5, 5), \
128 [_name##_##6] = REG_FIELD(_offset, 6, 6), \
129 [_name##_##7] = REG_FIELD(_offset, 7, 7), \
130 [_name##_##8] = REG_FIELD(_offset, 8, 8), \
131 [_name##_##9] = REG_FIELD(_offset, 9, 9), \
137 [_name##_##15] = REG_FIELD(_offset, 15, 15)
[all …]
/drivers/clk/bcm/
A Dclk-kona.h93 .offset = (_offset), \
153 .offset = (_offset), \
165 .offset = (_offset), \
176 .offset = (_offset), \
187 .offset = (_offset), \
197 .offset = (_offset), \
213 .offset = (_offset), \
344 .offset = (_offset), \
377 .offset = (_offset), \
436 .offset = (_offset), \
[all …]
/drivers/net/ethernet/mellanox/mlxsw/
A Dcore_acl_flex_keys.h61 .offset = _offset, \
70 _element, _offset, _shift, _size)
72 #define MLXSW_AFK_ELEMENT_INFO_BUF(_element, _offset, _size) \ argument
74 _element, _offset, 0, _size)
88 #define MLXSW_AFK_ELEMENT_INST(_type, _element, _offset, \ argument
94 .offset = _offset, \
105 _element, _offset, _shift, _size, 0, false)
107 #define MLXSW_AFK_ELEMENT_INST_EXT_U32(_element, _offset, \ argument
111 _element, _offset, _shift, _size, \
114 #define MLXSW_AFK_ELEMENT_INST_BUF(_element, _offset, _size) \ argument
[all …]
A Ditem.h272 .offset = _offset, \
291 .offset = _offset, \
315 .offset = _offset, \
334 .offset = _offset, \
358 .offset = _offset, \
413 .offset = _offset, \
437 .offset = _offset, \
456 .offset = _offset, \
480 .offset = _offset, \
505 .offset = _offset, \
[all …]
/drivers/clk/tegra/
A Dclk-tegra-periph.c132 #define MUX(_name, _parents, _offset, \ argument
146 #define MUX8(_name, _parents, _offset, \ argument
165 #define INT(_name, _parents, _offset, \ argument
179 #define INT8(_name, _parents, _offset,\ argument
186 #define UART(_name, _parents, _offset,\ argument
193 #define UART8(_name, _parents, _offset,\ argument
200 #define I2C(_name, _parents, _offset,\ argument
217 _offset, 16, 0xE01F, 0, 0, 8, 1, \
248 .offset = _offset, \
842 .offset = _offset,\
[all …]
A Dclk-tegra-audio.c52 #define AUDIO(_name, _offset) \ argument
56 .offset = _offset,\
71 #define AUDIO2X(_name, _num, _offset) \ argument
79 .div_offset = _offset,\
/drivers/clk/renesas/
A Drcar-gen3-cpg.h37 #define DEF_GEN3_SDH(_name, _id, _parent, _offset) \ argument
38 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset)
40 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
41 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
60 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ argument
61 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
A Drcar-gen4-cpg.h35 #define DEF_GEN4_SDH(_name, _id, _parent, _offset) \ argument
36 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset)
38 #define DEF_GEN4_SD(_name, _id, _parent, _offset) \ argument
39 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
61 #define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \ argument
62 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
A Drzv2h-cpg.h25 #define PLL_PACK(_offset, _has_clkn) \ argument
27 .offset = _offset, \
60 #define DDIV_PACK(_offset, _shift, _width, _monbit) \ argument
62 .offset = _offset, \
68 #define DDIV_PACK_NO_RMW(_offset, _shift, _width, _monbit) \ argument
70 .offset = (_offset), \
90 #define SMUX_PACK(_offset, _shift, _width) \ argument
92 .offset = (_offset), \
A Drenesas-cpg-mssr.h80 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
81 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
82 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument
83 DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
/drivers/bcma/
A Dsprom.c185 #define SPEX(_field, _offset, _mask, _shift) \ argument
188 #define SPEX32(_field, _offset, _mask, _shift) \ argument
190 sprom[SPOFF(_offset)]) & (_mask)) >> (_shift))
194 SPEX(_field[0], _offset + 0, _mask, _shift); \
195 SPEX(_field[1], _offset + 2, _mask, _shift); \
196 SPEX(_field[2], _offset + 4, _mask, _shift); \
197 SPEX(_field[3], _offset + 6, _mask, _shift); \
198 SPEX(_field[4], _offset + 8, _mask, _shift); \
199 SPEX(_field[5], _offset + 10, _mask, _shift); \
200 SPEX(_field[6], _offset + 12, _mask, _shift); \
[all …]
/drivers/pinctrl/mediatek/
A Dpinctrl-mtk-common.h109 #define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \ argument
112 .offset = _offset, \
134 #define MTK_PIN_PUPD_SPEC_SR(_pin, _offset, _pupd, _r1, _r0) \ argument
137 .offset = _offset, \
157 #define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \ argument
162 .offset = _offset, \
/drivers/clk/sunxi-ng/
A Dccu_mult.h17 #define _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, _min, _max) \ argument
21 .offset = _offset, \
29 #define _SUNXI_CCU_MULT_OFFSET(_shift, _width, _offset) \ argument
30 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, 1, 0)
/drivers/clk/mediatek/
A Dclk-mt6795-apmixedsys.c76 #define _FH(_pllid, _fhid, _slope, _offset) { \ argument
81 .fhx_offset = _offset, \
99 #define FH(_pllid, _fhid, _offset) _FH(_pllid, _fhid, 0x6003c97, _offset) argument
100 #define FH_M(_pllid, _fhid, _offset) _FH(_pllid, _fhid, 0x6000140, _offset) argument
/drivers/clk/sprd/
A Ddiv.h28 #define _SPRD_DIV_CLK(_offset, _shift, _width) \ argument
30 .offset = _offset, \
40 #define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _offset, \ argument
43 .div = _SPRD_DIV_CLK(_offset, _shift, _width), \
/drivers/clk/
A Dclk-loongson2.c61 #define CLK_DIV(_id, _name, _pname, _offset, _dshift, _dwidth) \ argument
67 .reg_offset = _offset, \
72 #define CLK_PLL(_id, _name, _offset, _mshift, _mwidth, \ argument
79 .reg_offset = _offset, \
86 #define CLK_SCALE(_id, _name, _pname, _offset, \ argument
93 .reg_offset = _offset, \
98 #define CLK_GATE(_id, _name, _pname, _offset, _bidx) \ argument
104 .reg_offset = _offset, \
A Dclk-loongson1.c153 #define LS1X_CLK_PLL(_name, _offset, _fixed, _shift, \ argument
156 .offset = (_offset), \
177 #define LS1X_CLK_DIV(_name, _pname, _offset, _shift, _width, \ argument
180 .offset = (_offset), \
/drivers/dpll/zl3073x/
A Dregs.h47 #define ZL_REG_IDX(_idx, _page, _offset, _size, _items, _stride) \ argument
49 (_offset) + (_idx) * (_stride)) | \
53 (_offset) + ((_items) - 1) * (_stride)))
63 #define ZL_REG(_page, _offset, _size) \ argument
64 ZL_REG_IDX(0, _page, _offset, _size, 1, 0)
/drivers/ssb/
A Dpci.c171 #define SPEX16(_outvar, _offset, _mask, _shift) \ argument
173 #define SPEX32(_outvar, _offset, _mask, _shift) \ argument
175 in[SPOFF(_offset)]) & (_mask)) >> (_shift))
176 #define SPEX(_outvar, _offset, _mask, _shift) \ argument
177 SPEX16(_outvar, _offset, _mask, _shift)
181 SPEX(_field[0], _offset + 0, _mask, _shift); \
182 SPEX(_field[1], _offset + 2, _mask, _shift); \
183 SPEX(_field[2], _offset + 4, _mask, _shift); \
184 SPEX(_field[3], _offset + 6, _mask, _shift); \
185 SPEX(_field[4], _offset + 8, _mask, _shift); \
[all …]
/drivers/clk/microchip/
A Dclk-mpfs.c136 #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ argument
141 .reg_offset = _offset, \
175 #define CLK_PLL_OUT(_id, _name, _parent, _flags, _shift, _width, _offset) { \ argument
180 .reg_offset = _offset, \
223 #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ argument
228 .reg_offset = _offset, \
A Dclk-mpfs-ccc.c101 #define CLK_CCC_PLL(_id, _parents, _shift, _width, _flags, _offset) { \ argument
105 .reg_offset = _offset, \
124 #define CLK_CCC_OUT(_id, _shift, _width, _flags, _offset) { \ argument
128 .reg_offset = _offset, \
/drivers/pinctrl/sophgo/
A Dpinctrl-sg2042.h40 #define SG2042_GENERAL_PIN(_id, _offset, _flag) \ argument
46 .offset = (_offset), \
/drivers/pinctrl/berlin/
A Dberlin.h31 #define BERLIN_PINCTRL_GROUP(_name, _offset, _width, _lsb, ...) \ argument
34 .offset = _offset, \
/drivers/clk/st/
A Dclkgen.h38 #define CLKGEN_FIELD(_offset, _mask, _shift) { \ argument
39 .offset = _offset, \
/drivers/clk/stm32/
A Dclk-stm32mp13.c140 #define _CFG_GATE(_id, _offset, _bit_idx, _offset_clr)\ argument
142 .offset = (_offset),\
147 #define CFG_GATE(_id, _offset, _bit_idx)\ argument
148 _CFG_GATE(_id, _offset, _bit_idx, 0)
150 #define CFG_GATE_SETCLR(_id, _offset, _bit_idx)\ argument
151 _CFG_GATE(_id, _offset, _bit_idx, RCC_CLR_OFFSET)
292 .offset = (_offset),\
354 .offset = (_offset),\
361 #define CFG_MUX(_id, _offset, _shift, _witdh)\ argument
364 #define CFG_MUX_SAFE(_id, _offset, _shift, _witdh)\ argument
[all …]

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