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/drivers/net/ethernet/amd/xgbe/
A Dxgbe-common.h1423 _reg##_##_field##_INDEX, \
1424 _reg##_##_field##_WIDTH)
1433 _reg##_##_field##_INDEX, \
1448 _reg##_##_field##_INDEX, \
1449 _reg##_##_field##_WIDTH)
1474 _reg##_##_field##_WIDTH)
1532 _reg##_##_field##_WIDTH)
1552 _reg##_##_field##_WIDTH)
1575 _reg##_##_field##_WIDTH)
1608 _reg##_##_field##_WIDTH)
[all …]
/drivers/clk/sprd/
A Dgate.h41 .reg = _reg, \
50 SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
56 SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \
66 #define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \ argument
68 SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, 0, \
75 SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \
100 SPRD_SC_GATE_CLK_HW_OPS(_struct, _name, _parent, _reg, \
104 #define SPRD_GATE_CLK_HW(_struct, _name, _parent, _reg, \ argument
119 _reg, _sc_offset, \ argument
131 _reg, _sc_offset, \
[all …]
A Dcomposite.h29 .reg = _reg, \
35 #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \ argument
37 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
41 #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \ argument
43 SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, NULL, \
49 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
54 #define SPRD_COMP_CLK_DATA(_struct, _name, _parent, _reg, _mshift, \ argument
56 SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, NULL, \
64 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
69 #define SPRD_COMP_CLK_DATA_OFFSET(_struct, _name, _parent, _reg, \ argument
[all …]
A Dpll.h64 #define SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument
79 .reg = _reg, \
85 #define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ argument
88 SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
92 #define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \ argument
95 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
99 #define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \ argument
101 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
105 #define SPRD_PLL_FW_NAME(_struct, _name, _parent, _reg, _regs_num, \ argument
108 SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
[all …]
A Dmux.h40 _reg, _shift, _width, _flags, _fn) \ argument
45 .reg = _reg, \
52 _reg, _shift, _width, _flags) \ argument
54 _reg, _shift, _width, _flags, \
57 #define SPRD_MUX_CLK(_struct, _name, _parents, _reg, \ argument
60 _reg, _shift, _width, _flags)
63 _reg, _shift, _width, _flags) \ argument
65 _reg, _shift, _width, _flags, \
68 #define SPRD_MUX_CLK_DATA(_struct, _name, _parents, _reg, \ argument
71 _reg, _shift, _width, _flags)
A Ddiv.h40 #define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _offset, \ argument
46 .reg = _reg, \
52 #define SPRD_DIV_CLK(_struct, _name, _parent, _reg, \ argument
54 SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, 0x0, \
57 #define SPRD_DIV_CLK_FW_NAME(_struct, _name, _parent, _reg, \ argument
59 SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, 0x0, \
62 #define SPRD_DIV_CLK_HW(_struct, _name, _parent, _reg, \ argument
64 SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, 0x0, \
/drivers/clk/sophgo/
A Dclk-cv18xx-pll.h50 #define PLL_GET_PRE_DIV_SEL(_reg) \ argument
52 #define PLL_GET_POST_DIV_SEL(_reg) \ argument
54 #define PLL_GET_SEL_MODE(_reg) \ argument
55 FIELD_GET(_PLL_SEL_MODE_FIELD, (_reg))
56 #define PLL_GET_DIV_SEL(_reg) \ argument
57 FIELD_GET(_PLL_DIV_SEL_FIELD, (_reg))
58 #define PLL_GET_ICTRL(_reg) \ argument
59 FIELD_GET(_PLL_ICTRL_FIELD, (_reg))
65 #define PLL_SET_SEL_MODE(_reg, _val) \ argument
67 #define PLL_SET_DIV_SEL(_reg, _val) \ argument
[all …]
A Dclk-cv18xx-common.h45 #define CV1800_CLK_BIT(_reg, _shift) \ argument
47 .reg = _reg, \
53 .reg = _reg, \
60 #define cv1800_clk_regfield_genmask(_reg) \ argument
61 GENMASK((_reg)->shift + (_reg)->width - 1, (_reg)->shift)
62 #define cv1800_clk_regfield_get(_val, _reg) \ argument
63 (((_val) >> (_reg)->shift) & GENMASK((_reg)->width - 1, 0))
64 #define cv1800_clk_regfield_set(_val, _new, _reg) \ argument
65 (((_val) & ~cv1800_clk_regfield_genmask((_reg))) | \
66 (((_new) & GENMASK((_reg)->width - 1, 0)) << (_reg)->shift))
[all …]
/drivers/clk/sunxi-ng/
A Dccu_div.h95 .reg = _reg, \
118 .reg = _reg, \
129 _reg, \ argument
138 .reg = _reg, \
148 _reg, \ argument
157 .reg = _reg, \
171 _reg, _mshift, _mwidth, \
202 .reg = _reg, \
224 .reg = _reg, \
249 .reg = _reg, \
[all …]
A Dccu_mp.h46 .reg = _reg, \
56 _reg, \ argument
68 .reg = _reg, \
88 .reg = _reg, \
101 SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
120 .reg = _reg, \
141 .reg = _reg, \
156 _reg, _mshift, _mwidth, \
167 _reg, _mshift, _mwidth, \
195 .reg = _reg, \
[all …]
A Dccu_gate.h19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
23 .reg = _reg, \
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
35 .reg = _reg, \
43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
47 .reg = _reg, \
63 .reg = _reg, \
71 #define SUNXI_CCU_GATE_HWS_WITH_PREDIV(_struct, _name, _parent, _reg, \ argument
76 .reg = _reg, \
90 .reg = _reg, \
[all …]
A Dccu_mux.h50 _reg, _shift, _width, _gate, \ argument
56 .reg = _reg, \
66 _table, _reg, _shift, \ argument
69 _table, _reg, _shift, \
74 _reg, _shift, _width, _gate, \ argument
77 _table, _reg, _shift, \
83 _reg, _shift, _width, _gate, \
89 _reg, _shift, _width, 0, _flags)
97 .reg = _reg, \
105 #define SUNXI_CCU_MUX_DATA(_struct, _name, _parents, _reg, \ argument
[all …]
A Dccu_nm.h52 .reg = _reg, \
76 .reg = _reg, \
86 _reg, _min_rate, \ argument
102 .reg = _reg, \
112 _parent, _reg, \ argument
132 .reg = _reg, \
142 _parent, _reg, \ argument
151 _parent, _reg, \
162 _parent, _reg, \ argument
171 _parent, _reg, \
[all …]
/drivers/regulator/
A Dmc13xxx.h66 .reg = prefix ## _reg, \
67 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
73 #define MC13xxx_FIXED_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ argument
84 .reg = prefix ## _reg, \
85 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
88 #define MC13xxx_GPO_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ argument
99 .reg = prefix ## _reg, \
100 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
103 #define MC13xxx_DEFINE_SW(_name, _node, _reg, _vsel_reg, _voltages, ops) \ argument
104 MC13xxx_DEFINE(SW, _name, _node, _reg, _vsel_reg, _voltages, ops)
[all …]
/drivers/clk/pistachio/
A Dclk.h19 #define GATE(_id, _name, _pname, _reg, _shift) \ argument
22 .reg = _reg, \
39 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument
42 .reg = _reg, \
59 #define DIV(_id, _name, _pname, _reg, _width) \ argument
62 .reg = _reg, \
72 .reg = _reg, \
119 #define PLL(_id, _name, _pname, _type, _reg, _rates) \ argument
122 .reg_base = _reg, \
130 #define PLL_FIXED(_id, _name, _pname, _type, _reg) \ argument
[all …]
/drivers/clk/meson/
A Daxg-audio.c82 .offset = (_reg), \
96 .offset = (_reg), \
112 .offset = (_reg), \
128 .offset = (_reg), \
143 .reg_off = (_reg), \
148 .reg_off = (_reg), \
166 .reg_off = (_reg), \
171 .reg_off = (_reg), \
176 .reg_off = (_reg), \
193 .reg_off = (_reg), \
[all …]
A Dclk-regmap.h121 #define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ argument
124 .offset = (_reg), \
136 #define MESON_PCLK(_name, _reg, _bit, _pname) \ argument
137 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname)
139 #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ argument
140 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname)
/drivers/clk/mediatek/
A Dclk-mtk.h112 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ argument
116 .mux_reg = _reg, \
119 .gate_reg = _reg, \
132 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument
134 MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \
142 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
145 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
146 MUX_FLAGS(_id, _name, _parents, _reg, \
152 .mux_reg = _reg, \
196 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
[all …]
/drivers/clk/x86/
A Dclk-cgu.h118 _reg, _type) \ argument
125 .reg = _reg, \
157 .reg = _reg, \
203 #define LGM_MUX(_id, _name, _pdata, _f, _reg, \ argument
212 .mux_off = _reg, \
231 .div_off = _reg, \
241 #define LGM_GATE(_id, _name, _pname, _f, _reg, \ argument
253 .gate_off = _reg, \
259 #define LGM_FIXED(_id, _name, _pname, _f, _reg, \ argument
271 .div_off = _reg, \
[all …]
/drivers/dpll/zl3073x/
A Dregs.h30 #define ZL_REG_OFFSET(_reg) FIELD_GET(ZL_REG_OFFSET_MASK, _reg) argument
31 #define ZL_REG_PAGE(_reg) FIELD_GET(ZL_REG_PAGE_MASK, _reg) argument
32 #define ZL_REG_MAX_OFFSET(_reg) FIELD_GET(ZL_REG_MAX_OFFSET_MASK, _reg) argument
33 #define ZL_REG_SIZE(_reg) FIELD_GET(ZL_REG_SIZE_MASK, _reg) argument
34 #define ZL_REG_ADDR(_reg) FIELD_GET(ZL_REG_ADDR_MASK, _reg) argument
/drivers/clk/actions/
A Dowl-pll.h41 #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ argument
44 .reg = _reg, \
55 #define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx, \ argument
58 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
70 #define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx, \ argument
73 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
84 #define OWL_PLL_NO_PARENT_DELAY(_struct, _name, _reg, _bfreq, _bit_idx, \ argument
88 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
A Dowl-gate.h27 #define OWL_GATE_HW(_reg, _bit_idx, _gate_flags) \ argument
29 .reg = _reg, \
34 #define OWL_GATE(_struct, _name, _parent, _reg, \ argument
37 .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \
47 #define OWL_GATE_NO_PARENT(_struct, _name, _reg, \ argument
50 .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \
/drivers/media/tuners/
A Dmc44s803_priv.h179 #define MC44S803_REG_SM(_val, _reg) \ argument
180 (((_val) << _reg##_S) & (_reg))
183 #define MC44S803_REG_MS(_val, _reg) \ argument
184 (((_val) & (_reg)) >> _reg##_S)
/drivers/gpu/drm/i915/gvt/
A Dreg.h76 #define REG_50080_TO_PIPE(_reg) ({ \ argument
77 typeof(_reg) (reg) = (_reg); \
83 #define REG_50080_TO_PLANE(_reg) ({ \ argument
84 typeof(_reg) (reg) = (_reg); \
/drivers/net/wireless/ath/ath5k/
A Dath5k.h126 (((_val) << _flags##_S) & (_flags)), _reg)
130 (_mask)) | (_flags), _reg)
133 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
136 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
139 #define AR5K_REG_READ_Q(ah, _reg, _queue) \ argument
140 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
142 #define AR5K_REG_WRITE_Q(ah, _reg, _queue) \ argument
143 ath5k_hw_reg_write(ah, (1 << _queue), _reg)
145 #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \ argument
146 _reg |= 1 << _queue; \
[all …]

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