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Searched refs:a (Results 1 – 25 of 1968) sorted by relevance

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/drivers/net/ethernet/marvell/octeontx2/af/
A Drvu_reg.h261 #define NIX_AF_RX_LINKX_CFG(a) (0x0540 | (a) << 16) argument
399 #define NIX_AF_LFX_CFG(a) (0x4000 | (a) << 17) argument
400 #define NIX_AF_LFX_SQS_CFG(a) (0x4020 | (a) << 17) argument
407 #define NIX_AF_LFX_TX_CFG(a) (0x4080 | (a) << 17) argument
409 #define NIX_AF_LFX_RX_CFG(a) (0x40A0 | (a) << 17) argument
432 #define NIX_AF_LINKX_CFG(a) (0x4010 | (a) << 17) argument
434 #define NIX_AF_SMQX_STATUS(a) (0x730 | (a) << 16) argument
583 #define NPC_AF_KPUX_CFG(a) (0x00500 | (a) << 3) argument
607 #define NPC_AF_CPIX_CFG(a) (0x200000 | (a) << 3) argument
715 #define NDC_AF_BP_TEST(a) (0x00200 | (a) << 3) argument
[all …]
A Dmcs_reg.h93 #define MCSX_PAB_TX_SLAVE_PORT_CFGX(a) (0x2930ull + (a) * 0x40ull) argument
96 #define MCSX_PEX_RX_SLAVE_VLAN_CFGX(a) (0x3b58ull + (a) * 0x8ull) argument
97 #define MCSX_PEX_TX_SLAVE_VLAN_CFGX(a) (0x46f8ull + (a) * 0x8ull) argument
99 #define MCSX_PEX_TX_SLAVE_PORT_CONFIG(a) (0x4738ull + (a) * 0x8ull) argument
100 #define MCSX_PEX_RX_SLAVE_PORT_CFGX(a) (0x3b98ull + (a) * 0x8ull) argument
268 #define MCSX_PEX_RX_SLAVE_CUSTOM_TAGX(a) (0x4c8ull + (a) * 0x8ull) argument
269 #define MCSX_PEX_TX_SLAVE_CUSTOM_TAGX(a) (0x748ull + (a) * 0x8ull) argument
278 #define MCSX_PAB_RX_SLAVE_FIFO_SKID_CFGX(a) (0x290ull + (a) * 0x40ull) argument
602 #define MCSX_CPM_TX_SLAVE_TX_SA_ACTIVEX(a) (0x5b50 + (a) * 0x8ull) argument
603 #define MCSX_CPM_TX_SLAVE_SA_INDEX0_VLDX(a) (0x5d50 + (a) * 0x8ull) argument
[all …]
/drivers/scsi/esas2r/
A Desas2r_init.c241 a->pcid->irq, a, a->name, flags); in esas2r_claim_interrupts()
249 a)) { in esas2r_claim_interrupts()
392 memset(a->uncached, 0, a->uncached_size); in esas2r_init_adapter()
429 a, a->disable_cnt); in esas2r_init_adapter()
495 free_irq(a->pcid->irq, a); in esas2r_adapter_power_down()
677 esas2r_setup_interrupts(a, a->intr_mode); in esas2r_resume()
778 if (!alloc_vda_req(a, &a->general_req)) { in esas2r_init_adapter_struct()
856 a->inbound_list_md.size = a->list_size * in esas2r_init_adapter_struct()
866 a->outbound_list_md.size = a->list_size * in esas2r_init_adapter_struct()
1055 ((u8 *)a->outbound_copy - a->uncached); in esas2r_check_adapter()
[all …]
A Desas2r_int.c100 esas2r_schedule_tasklet(a); in esas2r_interrupt()
222 rspget_ptr = a->last_read; in esas2r_get_outbound_responses()
425 *a->outbound_copy = in esas2r_process_adapter_reset()
426 a->last_write = in esas2r_process_adapter_reset()
427 a->last_read = a->list_size - 1; in esas2r_process_adapter_reset()
499 if (!esas2r_is_adapter_present(a) || (a->chip_uptime >= in esas2r_chip_rst_needed_during_tasklet()
517 a->int_mask = 0; in esas2r_chip_rst_needed_during_tasklet()
540 esas2r_reset_chip(a); in esas2r_chip_rst_needed_during_tasklet()
551 a->prev_dev_cnt = in esas2r_chip_rst_needed_during_tasklet()
557 a->int_mask = 0; in esas2r_chip_rst_needed_during_tasklet()
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A Desas2r_disc.c116 a->disc_wait_time = 0; in esas2r_disc_initialize()
125 a->disc_wait_cnt = a->prev_dev_cnt; in esas2r_disc_initialize()
203 if (a->disc_wait_time) { in esas2r_disc_check_complete()
212 && (esas2r_targ_db_get_tgt_cnt(a) < a->disc_wait_cnt in esas2r_disc_check_complete()
259 a->disc_wait_time = 0; in esas2r_disc_check_complete()
528 esas2r_build_mgt_req(a, in esas2r_disc_block_dev_scan()
603 esas2r_build_mgt_req(a, in esas2r_disc_raid_grp_info()
714 esas2r_build_mgt_req(a, in esas2r_disc_part_info()
1039 + (u64)((u8 *)a->disc_buffer - a->uncached); in esas2r_disc_get_phys_addr()
1056 for (t = a->targetdb; t < a->targetdb_end; t++) { in esas2r_disc_dev_remove()
[all …]
A Desas2r_ioctl.c127 a->firmware.header_buff = dma_alloc_coherent(&a->pcid->dev, in do_fm_api()
144 a->save_offset = a->firmware.header_buff; in do_fm_api()
155 a->fm_api_sgc.cur_offset = a->save_offset; in do_fm_api()
209 struct esas2r_adapter *a = bi->a; in handle_buffered_ioctl() local
320 bi.a = a; in handle_smp_ioctl()
654 bi.a = a; in handle_csmi_ioctl()
1231 bi.a = a; in handle_hba_ioctl()
1546 a->firmware.data = dma_alloc_coherent(&a->pcid->dev, in allocate_fw_buffers()
1603 do_fm_api(a, &a->firmware.header); in esas2r_read_fw()
1892 a->vda_buffer = dma_alloc_coherent(&a->pcid->dev, in esas2r_write_vda()
[all …]
A Desas2r.h147 #define esas2r_flush_register_dword(a, r) esas2r_read_register_dword(a, r) argument
776 struct esas2r_adapter *a; member
1163 struct esas2r_adapter *a, in esas2r_sgc_init() argument
1167 sgc->adapter = a; in esas2r_sgc_init()
1196 struct esas2r_adapter *a) in esas2r_rq_init_request() argument
1305 return (*a->build_sgl)(a, sgc); in esas2r_build_sg_list()
1353 esas2r_disable_heartbeat(a); in esas2r_local_reset_adapter()
1365 if (a->int_mask == 0) in esas2r_adapter_interrupt_pending()
1375 a->int_stat = intstat; in esas2r_adapter_interrupt_pending()
1376 a->int_mask = 0; in esas2r_adapter_interrupt_pending()
[all …]
A Desas2r_io.c148 a->last_write++; in esas2r_start_vda_request()
149 if (a->last_write >= a->list_size) { in esas2r_start_vda_request()
150 a->last_write = 0; in esas2r_start_vda_request()
161 + a->last_write; in esas2r_start_vda_request()
171 dw = a->last_write; in esas2r_start_vda_request()
231 sgl = esas2r_alloc_sgl(a); in esas2r_build_sg_list_sge()
449 sgl = esas2r_alloc_sgl(a); in esas2r_build_prd_iblk()
683 esas2r_force_interrupt(a); in esas2r_handle_pending_reset()
694 a->max_vdareq_size = 128; in esas2r_handle_pending_reset()
719 if (a->chip_uptime && in esas2r_timer_tick()
[all …]
A Desas2r_main.c181 if (handle_hba_ioctl(a, a->local_atto_ioctl) != IOCTL_SUCCESS) in read_hw()
672 a->fw_rev[0] ? a->fw_rev : "(none)"); in esas2r_show_info()
695 for (t = a->targetdb; t < a->targetdb_end; t++) in esas2r_show_info()
755 a->pcid->bus->number, a->pcid->devfn, a->pcid->irq, in esas2r_info()
756 a->fw_rev[0] ? a->fw_rev : "(none)"); in esas2r_info()
1588 struct esas2r_adapter *a = timer_container_of(a, t, timer); in esas2r_timer_callback() local
1606 struct esas2r_adapter *a = fw_event->a; in esas2r_free_fw_event() local
1652 &(a->host-> in esas2r_add_device()
1661 &(a->host-> in esas2r_add_device()
1792 struct esas2r_adapter *a = fw_event->a; in esas2r_firmware_event_work() local
[all …]
A Desas2r_targdb.c50 for (t = a->targetdb; t < a->targetdb_end; t++) { in esas2r_targ_db_initialize()
64 for (t = a->targetdb; t < a->targetdb_end; t++) { in esas2r_targ_db_remove_all()
74 a)); in esas2r_targ_db_remove_all()
76 a), in esas2r_targ_db_remove_all()
94 for (t = a->targetdb; t < a->targetdb_end; t++) { in esas2r_targ_db_report_changes()
106 a)); in esas2r_targ_db_report_changes()
143 a)); in esas2r_targ_db_add_raid()
237 for (t = a->targetdb; t < a->targetdb_end; t++) in esas2r_targ_db_find_by_sas_addr()
250 for (t = a->targetdb; t < a->targetdb_end; t++) { in esas2r_targ_db_find_by_ident()
281 for (t = a->targetdb; t < a->targetdb_end; t++) { in esas2r_targ_db_find_by_virt_id()
[all …]
A Desas2r_flash.c194 esas2r_build_flash_req(a, in build_flash_msg()
237 build_flash_msg(a, rq); in load_image()
1092 a->flash_ver = 0; in esas2r_print_flash_rev()
1197 if (!esas2r_read_flash_block(a, a->nvram, FLS_OFFSET_NVR, in esas2r_nvram_read_direct()
1273 n = a->nvram; in esas2r_nvram_write()
1300 n = a->nvram; in esas2r_nvram_write()
1316 a->uncached_phys + (u64)((u8 *)n - a->uncached)); in esas2r_nvram_write()
1321 a->uncached_phys in esas2r_nvram_write()
1434 fix_bios(a, fi); in esas2r_fm_api()
1440 fix_efi(a, fi); in esas2r_fm_api()
[all …]
/drivers/net/ethernet/marvell/octeontx2/nic/
A Dotx2_reg.h18 #define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3) argument
19 #define RVU_PF_VFME_STATUSX(a) (0x800 | (a) << 3) argument
20 #define RVU_PF_VFTRPENDX(a) (0x820 | (a) << 3) argument
21 #define RVU_PF_VFTRPEND_W1SX(a) (0x840 | (a) << 3) argument
22 #define RVU_PF_VFPF_MBOX_INTX(a) (0x880 | (a) << 3) argument
48 #define RVU_MBOX_PF_VFPF_INTX(a) (0x1000 | (a) << 3) argument
53 #define RVU_MBOX_PF_VFPF1_INTX(a) (0x1080 | (a) << 3) argument
61 #define RVU_VF_VFPF_MBOXX(a) (0x00 | (a) << 3) argument
67 #define RVU_VF_MSIX_VECX_ADDR(a) (0x000 | (a) << 4) argument
68 #define RVU_VF_MSIX_VECX_CTL(a) (0x008 | (a) << 4) argument
[all …]
/drivers/crypto/cavium/cpt/
A Dcpt_common.h39 #define CPTX_PF_CONSTANTS(a) (0x0ll + ((u64)(a) << 36)) argument
40 #define CPTX_PF_RESET(a) (0x100ll + ((u64)(a) << 36)) argument
41 #define CPTX_PF_DIAG(a) (0x120ll + ((u64)(a) << 36)) argument
42 #define CPTX_PF_BIST_STATUS(a) (0x160ll + ((u64)(a) << 36)) argument
43 #define CPTX_PF_ECC0_CTL(a) (0x200ll + ((u64)(a) << 36)) argument
44 #define CPTX_PF_ECC0_FLIP(a) (0x210ll + ((u64)(a) << 36)) argument
45 #define CPTX_PF_ECC0_INT(a) (0x220ll + ((u64)(a) << 36)) argument
46 #define CPTX_PF_ECC0_INT_W1S(a) (0x230ll + ((u64)(a) << 36)) argument
47 #define CPTX_PF_ECC0_ENA_W1S(a) (0x240ll + ((u64)(a) << 36)) argument
63 #define CPTX_PF_EXEC_INFO(a) (0x700ll + ((u64)(a) << 36)) argument
[all …]
/drivers/net/ethernet/marvell/octeontx2/af/cn20k/
A Dreg.h15 #define RVU_PRIV_PFX_DISC(a) (0x8000208 | (a) << 16) argument
16 #define RVU_PRIV_HWVFX_DISC(a) (0xD000000 | (a) << 12) argument
20 #define RVU_MBOX_AF_PFX_ADDR(a) (0x5000 | (a) << 4) argument
21 #define RVU_MBOX_AF_PFX_CFG(a) (0x6000 | (a) << 4) argument
22 #define RVU_MBOX_AF_AFPFX_TRIGX(a) (0x9000 | (a) << 3) argument
23 #define RVU_MBOX_AF_PFAF_INT(a) (0x2980 | (a) << 6) argument
24 #define RVU_MBOX_AF_PFAF_INT_W1S(a) (0x2988 | (a) << 6) argument
27 #define RVU_MBOX_AF_PFAF1_INT(a) (0x29A0 | (a) << 6) argument
33 #define RVU_MBOX_PF_PFAF_TRIGX(a) (0xC00 | (a) << 3) argument
41 #define NIX_CINTX_INT_W1S(a) (0xd30 | (a) << 12) argument
[all …]
/drivers/acpi/acpica/
A Dacmacros.h250 #define ACPI_FIND_LAST_BIT_8(a) ((a) ? __ACPI_FIND_LAST_BIT_8 (a, 1) : 0) argument
251 #define ACPI_FIND_LAST_BIT_16(a) ((a) ? __ACPI_FIND_LAST_BIT_16 (a, 1) : 0) argument
252 #define ACPI_FIND_LAST_BIT_32(a) ((a) ? __ACPI_FIND_LAST_BIT_32 (a, 1) : 0) argument
253 #define ACPI_FIND_LAST_BIT_64(a) ((a) ? __ACPI_FIND_LAST_BIT_64 (a, 1) : 0) argument
272 #define ACPI_FIND_FIRST_BIT_8(a) ((a) ? __ACPI_FIND_FIRST_BIT_8 (a, 1) : 0) argument
273 #define ACPI_FIND_FIRST_BIT_16(a) ((a) ? __ACPI_FIND_FIRST_BIT_16 (a, 1) : 0) argument
274 #define ACPI_FIND_FIRST_BIT_32(a) ((a) ? __ACPI_FIND_FIRST_BIT_32 (a, 1) : 0) argument
275 #define ACPI_FIND_FIRST_BIT_64(a) ((a) ? __ACPI_FIND_FIRST_BIT_64 (a, 1) : 0) argument
294 #define ACPI_IS_POWER_OF_TWO(a) ACPI_IS_ALIGNED(a, a) argument
398 #define ARGI_LIST1(a) (ARG_1(a)) argument
[all …]
/drivers/net/wireless/intel/iwlwifi/
A Diwl-debug.h181 #define IWL_DEBUG_RX(p, f, a...) IWL_DEBUG(p, IWL_DL_RX, f, ## a) argument
182 #define IWL_DEBUG_TX(p, f, a...) IWL_DEBUG(p, IWL_DL_TX, f, ## a) argument
183 #define IWL_DEBUG_ISR(p, f, a...) IWL_DEBUG(p, IWL_DL_ISR, f, ## a) argument
184 #define IWL_DEBUG_WEP(p, f, a...) IWL_DEBUG(p, IWL_DL_WEP, f, ## a) argument
185 #define IWL_DEBUG_HC(p, f, a...) IWL_DEBUG(p, IWL_DL_HCMD, f, ## a) argument
187 #define IWL_DEBUG_TE(p, f, a...) IWL_DEBUG(p, IWL_DL_TE, f, ## a) argument
190 #define IWL_DEBUG_FW(p, f, a...) IWL_DEBUG(p, IWL_DL_FW, f, ## a) argument
203 #define IWL_DEBUG_HT(p, f, a...) IWL_DEBUG(p, IWL_DL_HT, f, ## a) argument
213 #define IWL_DEBUG_11H(p, f, a...) IWL_DEBUG(p, IWL_DL_11H, f, ## a) argument
214 #define IWL_DEBUG_TPT(p, f, a...) IWL_DEBUG(p, IWL_DL_TPT, f, ## a) argument
[all …]
/drivers/gpu/drm/nouveau/include/nvhw/class/
A Dcl907d.h72 #define NV907D_DAC_SET_CONTROL(a) (0x00000180 + (a)*0… argument
83 #define NV907D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0… argument
106 #define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00000404 + (a)*0… argument
128 #define NV907D_HEAD_SET_CONTROL(a) (0x00000408 + (a)*0… argument
132 #define NV907D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000410 + (a)*0… argument
136 #define NV907D_HEAD_SET_RASTER_SIZE(a) (0x00000414 + (a)*0… argument
139 #define NV907D_HEAD_SET_RASTER_SYNC_END(a) (0x00000418 + (a)*0… argument
142 #define NV907D_HEAD_SET_RASTER_BLANK_END(a) (0x0000041C + (a)*0… argument
145 #define NV907D_HEAD_SET_RASTER_BLANK_START(a) (0x00000420 + (a)*0… argument
148 #define NV907D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000424 + (a)*0… argument
[all …]
A Dcl507d.h88 #define NV507D_DAC_SET_CONTROL(a) (0x00000400 + (a)*0… argument
122 #define NV507D_DAC_SET_POLARITY(a) (0x00000404 + (a)*0… argument
131 #define NV507D_SOR_SET_CONTROL(a) (0x00000600 + (a)*0… argument
160 #define NV507D_PIOR_SET_CONTROL(a) (0x00000700 + (a)*0… argument
183 #define NV507D_HEAD_SET_PIXEL_CLOCK(a) (0x00000804 + (a)*0… argument
195 #define NV507D_HEAD_SET_CONTROL(a) (0x00000808 + (a)*0… argument
199 #define NV507D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000810 + (a)*0… argument
203 #define NV507D_HEAD_SET_RASTER_SIZE(a) (0x00000814 + (a)*0… argument
206 #define NV507D_HEAD_SET_RASTER_SYNC_END(a) (0x00000818 + (a)*0… argument
209 #define NV507D_HEAD_SET_RASTER_BLANK_END(a) (0x0000081C + (a)*0… argument
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A Dclc57d.h30 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0… argument
82 #define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a) (0x00001008 + (a)*0… argument
134 #define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a) (0x00001010 + (a)*0… argument
149 #define NVC57D_HEAD_SET_PROCAMP(a) (0x00002000 + (a)*0… argument
161 #define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00002004 + (a)*0… argument
220 #define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x0000200C + (a)*0… argument
225 #define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x0000201C + (a)*0… argument
235 #define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00002028 + (a)*0… argument
240 #define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS(a) (0x00002030 + (a)*0… argument
256 #define NVC57D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0… argument
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A Dcl827d.h28 #define NV827D_HEAD_SET_BASE_LUT_LO(a) (0x00000840 + (a)*0… argument
36 #define NV827D_HEAD_SET_BASE_LUT_HI(a) (0x00000844 + (a)*0… argument
38 #define NV827D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000085C + (a)*0… argument
40 #define NV827D_HEAD_SET_OFFSET(a,b) (0x00000860 + (a)*0… argument
42 #define NV827D_HEAD_SET_SIZE(a) (0x00000868 + (a)*0… argument
45 #define NV827D_HEAD_SET_STORAGE(a) (0x0000086C + (a)*0… argument
57 #define NV827D_HEAD_SET_PARAMS(a) (0x00000870 + (a)*0… argument
76 #define NV827D_HEAD_SET_CONTEXT_DMAS_ISO(a,b) (0x00000874 + (a)*0… argument
78 #define NV827D_HEAD_SET_CONTROL_CURSOR(a) (0x00000880 + (a)*0… argument
99 #define NV827D_HEAD_SET_OFFSET_CURSOR(a) (0x00000884 + (a)*0… argument
[all …]
A Dclc37d.h204 #define NVC37D_SOR_SET_CONTROL(a) (0x00000300 + (a)*0… argument
232 #define NVC37D_WINDOW_SET_CONTROL(a) (0x00001000 + (a)*0… argument
245 #define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0… argument
297 #define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a) (0x00001008 + (a)*0… argument
349 #define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a) (0x00001010 + (a)*0… argument
362 #define NVC37D_HEAD_SET_PROCAMP(a) (0x00002000 + (a)*0… argument
383 #define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00002004 + (a)*0… argument
408 #define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x0000200C + (a)*0… argument
413 #define NVC37D_HEAD_SET_DITHER_CONTROL(a) (0x00002018 + (a)*0… argument
432 #define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00002028 + (a)*0… argument
[all …]
A Dclca7d.h211 #define NVCA7D_SOR_SET_CONTROL(a) (0x00000300 + (a)*0… argument
239 #define NVCA7D_WINDOW_SET_CONTROL(a) (0x00001000 + (a)*0… argument
261 #define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0… argument
313 #define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a) (0x00001008 + (a)*0… argument
365 #define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a) (0x00001010 + (a)*0… argument
386 #define NVCA7D_WINDOW_SET_PHYSICAL(a) (0x00001014 + (a)*0… argument
422 #define NVCA7D_HEAD_SET_PROCAMP(a) (0x00002000 + (a)*0… argument
437 #define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00002004 + (a)*0… argument
498 #define NVCA7D_HEAD_SET_CONTROL(a) (0x00002008 + (a)*0… argument
624 #define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x0000200C + (a)*0… argument
[all …]
/drivers/target/iscsi/
A Discsi_target_nodeattrib.c34 a->dataout_timeout = NA_DATAOUT_TIMEOUT; in iscsit_set_default_node_attribues()
36 a->nopin_timeout = NA_NOPIN_TIMEOUT; in iscsit_set_default_node_attribues()
40 a->random_r2t_offsets = NA_RANDOM_R2T_OFFSETS; in iscsit_set_default_node_attribues()
41 a->default_erl = tpg->tpg_attrib.default_erl; in iscsit_set_default_node_attribues()
62 a->dataout_timeout = dataout_timeout; in iscsit_na_dataout_timeout()
104 u32 orig_nopin_timeout = a->nopin_timeout; in iscsit_na_nopin_timeout()
118 a->nopin_timeout = nopin_timeout; in iscsit_na_nopin_timeout()
120 " Node %s\n", a->nopin_timeout, in iscsit_na_nopin_timeout()
170 " Initiator Node %s\n", a->nopin_timeout, in iscsit_na_nopin_response_timeout()
248 a->default_erl = default_erl; in iscsit_na_default_erl()
[all …]
/drivers/gpu/drm/i915/display/
A Dintel_display_reg_defs.h18 #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) argument
19 #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b) argument
20 #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b) argument
21 #define _PORT(port, a, b) _PICK_EVEN(port, a, b) argument
22 #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b) argument
23 #define _PHY(phy, a, b) _PICK_EVEN(phy, a, b) argument
25 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) argument
27 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) argument
28 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) argument
29 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) argument
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/drivers/gpu/drm/amd/display/dc/dml/
A Ddml_inline_defs.h34 return (double) dcn_bw_min2(a, b); in dml_min()
39 return dml_min(dml_min(a, b), c); in dml_min3()
49 return (double) dcn_bw_max2(a, b); in dml_max()
54 return dml_max(dml_max(a, b), c); in dml_max3()
81 static inline double dml_round(double a) in dml_round() argument
85 return dml_floor(a + round_pt, 1); in dml_round()
106 return (double) dcn_bw_pow(a, exp); in dml_pow()
152 static inline double dml_abs(double a) in dml_abs() argument
154 if (a > 0) in dml_abs()
155 return a; in dml_abs()
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