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/drivers/iommu/iommufd/
A Ddevice.c1104 access->ops->unmap(access->data, 0, ULONG_MAX); in iommufd_access_change_ioas()
1150 access = iommufd_object_alloc(ictx, access, IOMMUFD_OBJ_ACCESS); in __iommufd_access_create()
1152 return access; in __iommufd_access_create()
1157 return access; in __iommufd_access_create()
1166 return access; in iommufd_access_create_internal()
1170 return access; in iommufd_access_create_internal()
1194 return access; in iommufd_access_create()
1208 return access; in iommufd_access_create()
1220 iommufd_object_destroy_user(access->ictx, &access->obj); in iommufd_access_destroy()
1314 access->ops->unmap(access->data, iova, length); in iommufd_access_notify_unmap()
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A Dviommu.c253 struct iommufd_access *access, in iommufd_hw_queue_destroy_access() argument
272 if (hw_queue->access) in iommufd_hw_queue_destroy()
274 hw_queue->access, in iommufd_hw_queue_destroy()
295 struct iommufd_access *access; in iommufd_hw_queue_alloc_phys() local
320 if (IS_ERR(access)) { in iommufd_hw_queue_alloc_phys()
321 rc = PTR_ERR(access); in iommufd_hw_queue_alloc_phys()
343 return access; in iommufd_hw_queue_alloc_phys()
361 struct iommufd_access *access; in iommufd_hw_queue_alloc_ioctl() local
408 if (IS_ERR(access)) { in iommufd_hw_queue_alloc_ioctl()
409 rc = PTR_ERR(access); in iommufd_hw_queue_alloc_ioctl()
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/drivers/infiniband/sw/rxe/
A Drxe_mw.c61 if (unlikely((access & IB_ZERO_BASED))) { in rxe_check_bind_mw()
94 if (unlikely(mr->access & IB_ZERO_BASED)) { in rxe_check_bind_mw()
107 if (unlikely((access & in rxe_check_bind_mw()
116 if (access & IB_ZERO_BASED) { in rxe_check_bind_mw()
141 mw->access = access; in rxe_do_bind_mw()
172 int access = wqe->wr.wr.mw.access; in rxe_bind_mw() local
200 if (access & ~RXE_ACCESS_SUPPORTED_MW) { in rxe_bind_mw()
212 rxe_do_bind_mw(qp, wqe, mw, mr, access); in rxe_bind_mw()
252 mw->access = 0; in rxe_do_invalidate_mw()
303 (mw->length == 0) || ((access & mw->access) != access) || in rxe_lookup_mw()
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A Drxe_mr.c48 void rxe_mr_init(int access, struct rxe_mr *mr) in rxe_mr_init() argument
60 mr->access = access; in rxe_mr_init()
69 rxe_mr_init(access, mr); in rxe_mr_init_dma()
130 int access, struct rxe_mr *mr) in rxe_mr_init_user() argument
135 rxe_mr_init(access, mr); in rxe_mr_init_user()
337 int access, in copy_data() argument
385 mr = lookup_mr(pd, access, sge->lkey, in copy_data()
628 mr_pd(mr) != pd || ((access & mr->access) != access) || in lookup_mr()
651 remote = mr->access & RXE_ACCESS_REMOTE; in rxe_invalidate_mr()
691 u32 access = wqe->wr.wr.reg.access; in rxe_reg_fast_mr() local
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/drivers/gpu/drm/nouveau/nvkm/engine/dma/
A Duser.c87 args->v0.version, args->v0.target, args->v0.access, in nvkm_dmaobj_ctor()
90 dmaobj->access = args->v0.access; in nvkm_dmaobj_ctor()
120 switch (dmaobj->access) { in nvkm_dmaobj_ctor()
122 dmaobj->access = NV_MEM_ACCESS_VM; in nvkm_dmaobj_ctor()
125 dmaobj->access = NV_MEM_ACCESS_RO; in nvkm_dmaobj_ctor()
128 dmaobj->access = NV_MEM_ACCESS_WO; in nvkm_dmaobj_ctor()
131 dmaobj->access = NV_MEM_ACCESS_RW; in nvkm_dmaobj_ctor()
/drivers/platform/chrome/
A Dcros_ec_lpc_mec.c129 enum cros_ec_lpc_mec_emi_access_mode access, new_access; in cros_ec_lpc_io_bytes_mec() local
145 access = ACCESS_TYPE_BYTE; in cros_ec_lpc_io_bytes_mec()
147 access = ACCESS_TYPE_LONG_AUTO_INCREMENT; in cros_ec_lpc_io_bytes_mec()
154 cros_ec_lpc_mec_emi_write_address(offset, access); in cros_ec_lpc_io_bytes_mec()
182 if (new_access != access || in cros_ec_lpc_io_bytes_mec()
183 access != ACCESS_TYPE_LONG_AUTO_INCREMENT) { in cros_ec_lpc_io_bytes_mec()
184 access = new_access; in cros_ec_lpc_io_bytes_mec()
185 cros_ec_lpc_mec_emi_write_address(offset, access); in cros_ec_lpc_io_bytes_mec()
/drivers/acpi/numa/
A Dhmat.c343 u8 type, u32 value, int access) in hmat_update_target_access() argument
347 target->coord[access].read_latency = value; in hmat_update_target_access()
372 enum access_coordinate_class access) in hmat_update_target_coordinates() argument
387 coord->read_latency, access); in hmat_update_target_coordinates()
389 coord->write_latency, access); in hmat_update_target_coordinates()
391 coord->read_bandwidth, access); in hmat_update_target_coordinates()
393 coord->write_bandwidth, access); in hmat_update_target_coordinates()
794 if (access == ACCESS_COORDINATE_LOCAL || in hmat_update_target_attrs()
823 if ((access == ACCESS_COORDINATE_CPU || in hmat_update_target_attrs()
845 int access) in __hmat_register_target_initiators() argument
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/drivers/net/dsa/sja1105/
A Dsja1105_dynamic_config.c886 .access = OP_WRITE,
910 .access = (OP_WRITE | OP_DEL),
919 .access = OP_WRITE,
927 .access = OP_WRITE,
935 .access = OP_WRITE,
943 .access = OP_WRITE,
959 .access = OP_WRITE,
1003 .access = OP_WRITE,
1051 .access = OP_WRITE,
1274 if (!(ops->access & OP_READ)) in sja1105_dynamic_config_read()
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/drivers/dax/
A DKconfig3 tristate "DAX: direct access to differentiated memory"
9 tristate "Device DAX: direct access mapping device"
12 Support raw access to differentiated (persistence, bandwidth,
20 tristate "PMEM DAX: direct access to persistent memory"
24 Support raw access to persistent memory. Note that this
31 tristate "HMEM DAX: direct access to 'specific purpose' memory"
48 tristate "CXL DAX: direct access to CXL RAM regions"
56 instance is created to access that unmapped-by-default address range.
57 Per usual it can remain as dedicated access via a device interface, or
70 Support access to persistent, or other performance
/drivers/clocksource/
A Darm_arch_timer.c129 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) { in arch_timer_reg_write()
145 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { in arch_timer_reg_write()
159 arch_timer_reg_write_cp15(access, reg, val); in arch_timer_reg_write()
164 u32 arch_timer_reg_read(int access, enum arch_timer_reg reg, in arch_timer_reg_read() argument
169 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) { in arch_timer_reg_read()
178 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { in arch_timer_reg_read()
188 val = arch_timer_reg_read_cp15(access, reg); in arch_timer_reg_read()
427 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); in erratum_set_next_event_generic()
431 if (access == ARCH_TIMER_PHYS_ACCESS) { in erratum_set_next_event_generic()
751 if (access == ARCH_TIMER_PHYS_ACCESS) in set_next_event()
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/drivers/infiniband/core/
A Dumem_dmabuf.c120 int fd, int access, in ib_umem_dmabuf_get_with_dma_device() argument
152 umem->writable = ib_access_writable(access); in ib_umem_dmabuf_get_with_dma_device()
179 int fd, int access, in ib_umem_dmabuf_get() argument
183 offset, size, fd, access, ops); in ib_umem_dmabuf_get()
205 int fd, int access) in ib_umem_dmabuf_get_pinned_with_dma_device() argument
211 size, fd, access, in ib_umem_dmabuf_get_pinned_with_dma_device()
241 int access) in ib_umem_dmabuf_get_pinned() argument
244 offset, size, fd, access); in ib_umem_dmabuf_get_pinned()
A Dumem_odp.c135 int access) in ib_umem_odp_alloc_implicit() argument
140 if (access & IB_ACCESS_HUGETLB) in ib_umem_odp_alloc_implicit()
148 umem->writable = ib_access_writable(access); in ib_umem_odp_alloc_implicit()
235 unsigned long addr, size_t size, int access, in ib_umem_odp_get() argument
241 if (WARN_ON_ONCE(!(access & IB_ACCESS_ON_DEMAND))) in ib_umem_odp_get()
251 umem_odp->umem.writable = ib_access_writable(access); in ib_umem_odp_get()
257 if (access & IB_ACCESS_HUGETLB) in ib_umem_odp_get()
/drivers/misc/c2port/
A Dcore.c363 c2dev->access = !!status; in access_store()
367 if (c2dev->access) in access_store()
369 ops->access(c2dev, c2dev->access); in access_store()
370 if (c2dev->access) in access_store()
377 static DEVICE_ATTR_RW(access);
386 if (!c2dev->access) in c2port_store_reset()
423 if (!c2dev->access) in c2port_show_dev_id()
460 if (!c2dev->access) in c2port_show_rev_id()
488 if (!dev->access) in __c2port_store_flash_access()
942 c2dev->access = c2dev->flash_access = 0; in c2port_device_register()
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/drivers/iio/
A Dindustrialio-buffer.c154 if (!rb || !rb->access->read) in iio_buffer_read()
192 ret = rb->access->read(rb, n, buf); in iio_buffer_read()
203 if (buf->access->space_available) in iio_buffer_space_available()
222 if (!rb || !rb->access->write) in iio_buffer_write()
358 if (!buffer || !buffer->access || !buffer->access->remove_from) in iio_pop_from_buffer()
824 if (!buffer->access->enable) in iio_buffer_enable()
832 if (!buffer->access->disable) in iio_buffer_disable()
923 modes &= buffer->access->modes; in iio_verify_update()
1892 if (buffer->access->lock_queue) in iio_buffer_enqueue_dmabuf()
2183 if (!buffer->access->set_length) in __iio_buffer_alloc_sysfs_and_mask()
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/drivers/hwmon/pmbus/
A Dmax31785.c30 ktime_t access; /* Chip access time */ member
49 s64 delta = ktime_us_delta(ktime_get(), data->access); in max31785_wait()
64 driver_data->access = ktime_get(); in max31785_i2c_write_byte_data()
76 driver_data->access = ktime_get(); in max31785_i2c_read_word_data()
88 driver_data->access = ktime_get(); in _max31785_read_byte_data()
100 driver_data->access = ktime_get(); in _max31785_write_byte_data()
112 driver_data->access = ktime_get(); in _max31785_read_word_data()
124 driver_data->access = ktime_get(); in _max31785_write_word_data()
488 driver_data->access = ktime_get(); in max31785_probe()
/drivers/hwtracing/coresight/
A Dcoresight-catu.h75 return csdev_access_relaxed_read32(&drvdata->csdev->access, offset); \
80 csdev_access_relaxed_write32(&drvdata->csdev->access, val, offset); \
87 return csdev_access_relaxed_read_pair(&drvdata->csdev->access, lo_off, hi_off); \
92 csdev_access_relaxed_write_pair(&drvdata->csdev->access, val, lo_off, hi_off); \
A Dcoresight-core.c181 csa = &csdev->access; in coresight_claim_device_unlocked()
220 CS_UNLOCK(csdev->access.base); in coresight_claim_device()
222 CS_LOCK(csdev->access.base); in coresight_claim_device()
239 coresight_clear_self_claim_tag_unlocked(&csdev->access); in coresight_disclaim_device_unlocked()
255 CS_UNLOCK(csdev->access.base); in coresight_disclaim_device()
257 CS_LOCK(csdev->access.base); in coresight_disclaim_device()
1253 return csdev_access_read32(&csdev->access, offset); in coresight_read32()
1264 csdev_access_write32(&csdev->access, val, offset); in coresight_write32()
1274 return csdev_access_read64(&csdev->access, offset); in coresight_read64()
1285 csdev_access_write64(&csdev->access, val, offset); in coresight_write64()
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/drivers/fwctl/
A DKconfig3 tristate "fwctl device firmware access framework"
5 fwctl provides a userspace API for restricted access to communicate
16 MLX5 provides interface for the user process to access the debug and
29 to access the debug and configuration information of the AMD/Pensando
/drivers/firmware/qcom/
A DKconfig53 The QSEECOM interface allows, among other things, access to applications
55 which is required to access UEFI variables on certain systems. If
66 Various Qualcomm SoCs do not allow direct access to EFI variables.
72 provide user-space with access to EFI variables via efivarfs.
74 Select Y here to provide access to EFI variables on the aforementioned
/drivers/target/
A DKconfig14 subsystem logic for virtual LUN 0 access
23 access to Linux/Block devices using BIO
29 access to Linux/VFS struct file or struct block_device
36 passthrough access to Linux/SCSI device
/drivers/devfreq/event/
A Drockchip-dfi.c76 u64 access; member
221 res->c[i].access = readl_relaxed(dfi_regs + in rockchip_dfi_read_counters()
255 u32 access = 0, clock_cycles = 0; in rockchip_dfi_get_event() local
267 a = count.c[i].access - last->c[i].access; in rockchip_dfi_get_event()
270 if (a > access) { in rockchip_dfi_get_event()
271 access = a; in rockchip_dfi_get_event()
276 edata->load_count = access * 4; in rockchip_dfi_get_event()
305 res->c[i].access = dfi->total_count.c[i].access + in rockchip_ddr_perf_counters_add()
306 (u32)(now->c[i].access - last->c[i].access); in rockchip_ddr_perf_counters_add()
474 count += total.c[i].access * blen * dfi->buswidth[i]; in rockchip_ddr_perf_event_get_count()
/drivers/base/
A Dnode.c84 unsigned int access; member
152 enum access_coordinate_class access) in node_init_node_access() argument
158 if (access_node->access == access) in node_init_node_access()
165 access_node->access = access; in node_init_node_access()
170 if (dev_set_name(dev, "access%u", access)) in node_init_node_access()
217 enum access_coordinate_class access) in node_set_perf_attrs() argument
227 c = node_init_node_access(node, access); in node_set_perf_attrs()
242 if (access == ACCESS_COORDINATE_CPU) { in node_set_perf_attrs()
728 enum access_coordinate_class access) in register_memory_node_under_compute_node() argument
739 initiator = node_init_node_access(init_node, access); in register_memory_node_under_compute_node()
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/drivers/mtd/devices/
A DKconfig58 This enables access to AT45xxx DataFlash chips, using SPI.
86 This enables access to Microchip 23K256 SRAM chips, using SPI.
96 This enables access to Microchip 48L640 EERAM chips, using SPI.
109 This enables access to the non JEDEC SST25L SPI flash chips, used
135 Use this driver to access physical memory that the kernel proper
136 doesn't have access to, memory beyond the mem=xxx limit, nvram,
182 This provides an MTD device to access flash on powernv OPAL
184 firmware interface for flash access.
191 This provides an MTD device to access Intel Discrete Graphics
208 The driver provides access to G3 DiskOnChip, distributed by
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/drivers/net/ethernet/intel/idpf/
A Didpf_ptp.c418 enum idpf_ptp_access access; in idpf_ptp_settime64() local
422 access = adapter->ptp->set_dev_clk_time_access; in idpf_ptp_settime64()
423 if (access != IDPF_PTP_MAILBOX) in idpf_ptp_settime64()
475 enum idpf_ptp_access access; in idpf_ptp_adjtime() local
478 access = adapter->ptp->adj_dev_clk_time_access; in idpf_ptp_adjtime()
479 if (access != IDPF_PTP_MAILBOX) in idpf_ptp_adjtime()
517 enum idpf_ptp_access access; in idpf_ptp_adjfine() local
521 access = adapter->ptp->adj_dev_clk_time_access; in idpf_ptp_adjfine()
522 if (access != IDPF_PTP_MAILBOX) in idpf_ptp_adjfine()
898 else if (txq->cached_tstamp_caps->access) in idpf_ptp_get_txq_tstamp_capability()
/drivers/thermal/st/
A DKconfig13 tristate "STi series memory mapped access based thermal sensors"
21 SoCs. This thermal driver allows to access to general thermal framework
22 functionalities and to access to SoC sensor functionalities. This

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