| /drivers/pmdomain/actions/ |
| A D | owl-sps-helper.c | 17 int owl_sps_set_pg(void __iomem *base, u32 pwr_mask, u32 ack_mask, bool enable) in owl_sps_set_pg() argument
24 ack = val & ack_mask; in owl_sps_set_pg()
37 if ((val & ack_mask) == (enable ? ack_mask : 0)) in owl_sps_set_pg()
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| A D | owl-sps.c | 51 u32 pwr_mask, ack_mask; in owl_sps_set_power() local
53 ack_mask = BIT(pd->info->ack_bit); in owl_sps_set_power()
56 return owl_sps_set_pg(pd->sps->base, pwr_mask, ack_mask, enable); in owl_sps_set_power()
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| /drivers/gpu/drm/amd/display/dc/irq/dce80/ |
| A D | irq_service_dce80.c | 74 .ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
88 .ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
103 .ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
118 .ack_mask =\
134 .ack_mask =\
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| /drivers/gpu/drm/amd/display/dc/irq/dce60/ |
| A D | irq_service_dce60.c | 83 .ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
97 .ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
112 .ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
127 .ack_mask =\
143 .ack_mask =\
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| /drivers/gpu/drm/amd/display/dc/irq/dce110/ |
| A D | irq_service_dce110.c | 98 .ack_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK,\
112 .ack_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK,\
126 .ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
141 .ack_mask =\
157 .ack_mask =\
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| /drivers/gpu/drm/amd/display/dc/irq/ |
| A D | irq_service.c | 147 value = (value & ~info->ack_mask) | in dal_irq_service_ack_generic()
148 (info->ack_value & info->ack_mask); in dal_irq_service_ack_generic()
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| A D | irq_service.h | 53 uint32_t ack_mask; member
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| /drivers/pmdomain/rockchip/ |
| A D | pm-domains.c | 50 int ack_mask; member
123 .ack_mask = (ack), \
136 .ack_mask = (ack), \
149 .ack_mask = (ack), \
168 .ack_mask = (ack), \
188 .ack_mask = (ack), \
197 .ack_mask = (ack), \
401 target_ack = idle ? pd_info->ack_mask : 0; in rockchip_pmu_set_idle_request()
403 (val & pd_info->ack_mask) == target_ack, in rockchip_pmu_set_idle_request()
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| /drivers/gpu/drm/amd/display/dc/irq/dcn21/ |
| A D | irq_service_dcn21.c | 195 .ack_mask = \
209 .ack_mask = \
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| /drivers/gpu/drm/amd/display/dc/irq/dcn31/ |
| A D | irq_service_dcn31.c | 190 .ack_mask = \
204 .ack_mask = \
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| /drivers/gpu/drm/amd/display/dc/irq/dcn314/ |
| A D | irq_service_dcn314.c | 192 .ack_mask = \
206 .ack_mask = \
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| /drivers/gpu/drm/amd/display/dc/irq/dcn315/ |
| A D | irq_service_dcn315.c | 197 .ack_mask = \
211 .ack_mask = \
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| /drivers/gpu/drm/amd/display/dc/irq/dcn30/ |
| A D | irq_service_dcn30.c | 202 .ack_mask = \
216 .ack_mask = \
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| /drivers/gpu/drm/amd/display/dc/irq/dcn302/ |
| A D | irq_service_dcn302.c | 186 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
205 .ack_mask = \
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| /drivers/gpu/drm/amd/display/dc/irq/dcn351/ |
| A D | irq_service_dcn351.c | 168 REG_STRUCT[base + reg_num].ack_mask = \
182 REG_STRUCT[base].ack_mask = \
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| /drivers/gpu/drm/amd/display/dc/irq/dcn401/ |
| A D | irq_service_dcn401.c | 181 .ack_mask = \
195 .ack_mask = \
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| /drivers/gpu/drm/amd/display/dc/irq/dcn32/ |
| A D | irq_service_dcn32.c | 201 .ack_mask = \
215 .ack_mask = \
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| /drivers/gpu/drm/amd/display/dc/irq/dcn35/ |
| A D | irq_service_dcn35.c | 189 REG_STRUCT[base + reg_num].ack_mask = \
203 REG_STRUCT[base].ack_mask = \
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| /drivers/gpu/drm/amd/display/dc/irq/dcn36/ |
| A D | irq_service_dcn36.c | 167 REG_STRUCT[base + reg_num].ack_mask = \
181 REG_STRUCT[base].ack_mask = \
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| /drivers/gpu/drm/amd/display/dc/irq/dce120/ |
| A D | irq_service_dce120.c | 85 .ack_mask = \
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| /drivers/gpu/drm/amd/display/dc/irq/dcn303/ |
| A D | irq_service_dcn303.c | 129 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
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| /drivers/gpu/drm/amd/display/dc/irq/dcn201/ |
| A D | irq_service_dcn201.c | 134 .ack_mask = \
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| /drivers/gpu/drm/amd/display/dc/irq/dcn10/ |
| A D | irq_service_dcn10.c | 182 .ack_mask = \
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| /drivers/gpu/drm/amd/display/dc/irq/dcn20/ |
| A D | irq_service_dcn20.c | 185 .ack_mask = \
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| /drivers/accel/habanalabs/gaudi2/ |
| A D | gaudi2.c | 4615 u32 reg_base, val, ack_mask, timeout_usec = 100000; in gaudi2_verify_arc_running_mode() local
4622 ack_mask = ARC_FARM_ARC0_AUX_RUN_HALT_ACK_RUN_ACK_MASK; in gaudi2_verify_arc_running_mode()
4624 ack_mask = ARC_FARM_ARC0_AUX_RUN_HALT_ACK_HALT_ACK_MASK; in gaudi2_verify_arc_running_mode()
4627 val, ((val & ack_mask) == ack_mask), in gaudi2_verify_arc_running_mode()
|