| /drivers/gpu/drm/amd/display/dc/irq/dce80/ |
| A D | irq_service_dce80.c | 73 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
87 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
102 .ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
117 .ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
133 .ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
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| /drivers/gpu/drm/amd/display/dc/irq/dce60/ |
| A D | irq_service_dce60.c | 82 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
96 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
111 .ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
126 .ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
142 .ack_reg = mmLB ## reg_num ## _VBLANK_STATUS,\
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| /drivers/gpu/drm/amd/display/dc/irq/dce110/ |
| A D | irq_service_dce110.c | 97 .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
111 .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
125 .ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
140 .ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
156 .ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
|
| /drivers/irqchip/ |
| A D | irq-digicolor.c | 58 unsigned en_reg, unsigned ack_reg) in digicolor_set_gc() argument
64 gc->chip_types[0].regs.ack = ack_reg; in digicolor_set_gc()
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| /drivers/gpu/drm/amd/display/dc/irq/ |
| A D | irq_service.h | 52 uint32_t ack_reg; member
|
| A D | irq_service.c | 144 uint32_t addr = info->ack_reg; in dal_irq_service_ack_generic()
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| /drivers/gpu/drm/amd/display/dc/irq/dcn21/ |
| A D | irq_service_dcn21.c | 194 .ack_reg = SRI(reg2, block, reg_num),\
208 .ack_reg = SRI_DMUB(reg2),\
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| /drivers/gpu/drm/amd/display/dc/irq/dcn31/ |
| A D | irq_service_dcn31.c | 189 .ack_reg = SRI(reg2, block, reg_num),\
203 .ack_reg = SRI_DMUB(reg2),\
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| /drivers/gpu/drm/amd/display/dc/irq/dcn314/ |
| A D | irq_service_dcn314.c | 191 .ack_reg = SRI(reg2, block, reg_num),\
205 .ack_reg = SRI_DMUB(reg2),\
|
| /drivers/gpu/drm/amd/display/dc/irq/dcn315/ |
| A D | irq_service_dcn315.c | 196 .ack_reg = SRI(reg2, block, reg_num),\
210 .ack_reg = SRI_DMUB(reg2),\
|
| /drivers/gpu/drm/amd/display/dc/irq/dcn30/ |
| A D | irq_service_dcn30.c | 201 .ack_reg = SRI(reg2, block, reg_num),\
215 .ack_reg = SRI_DMUB(reg2),\
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| /drivers/gpu/drm/amd/display/dc/irq/dcn302/ |
| A D | irq_service_dcn302.c | 185 .ack_reg = SRI(reg2, block, reg_num),\
204 .ack_reg = SRI_DMUB(reg2),\
|
| /drivers/gpu/drm/amd/display/dc/irq/dcn351/ |
| A D | irq_service_dcn351.c | 167 REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
181 REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\
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| /drivers/gpu/drm/amd/display/dc/irq/dcn401/ |
| A D | irq_service_dcn401.c | 180 .ack_reg = SRI(reg2, block, reg_num),\
194 .ack_reg = SRI_DMUB(reg2),\
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| /drivers/gpu/drm/amd/display/dc/irq/dcn32/ |
| A D | irq_service_dcn32.c | 200 .ack_reg = SRI(reg2, block, reg_num),\
214 .ack_reg = SRI_DMUB(reg2),\
|
| /drivers/gpu/drm/amd/display/dc/irq/dcn35/ |
| A D | irq_service_dcn35.c | 188 REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
202 REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\
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| /drivers/gpu/drm/amd/display/dc/irq/dcn36/ |
| A D | irq_service_dcn36.c | 166 REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
180 REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\
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| /drivers/gpu/drm/i915/gt/ |
| A D | intel_reset.c | 369 i915_reg_t ack_reg; member
388 sfc_lock->ack_reg = GEN11_VCS_SFC_LOCK_STATUS(engine->mmio_base); in get_sfc_forced_lock_data()
400 sfc_lock->ack_reg = GEN11_VECS_SFC_LOCK_ACK(engine->mmio_base); in get_sfc_forced_lock_data()
472 sfc_lock.ack_reg, in gen11_lock_sfc()
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| /drivers/gpu/drm/amd/display/dc/irq/dce120/ |
| A D | irq_service_dce120.c | 84 .ack_reg = SRI(reg2, block, reg_num),\
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| /drivers/gpu/drm/amd/display/dc/irq/dcn303/ |
| A D | irq_service_dcn303.c | 128 .ack_reg = SRI(reg2, block, reg_num),\
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| /drivers/gpu/drm/amd/display/dc/irq/dcn201/ |
| A D | irq_service_dcn201.c | 133 .ack_reg = SRI(reg2, block, reg_num),\
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| /drivers/gpu/drm/amd/display/dc/irq/dcn10/ |
| A D | irq_service_dcn10.c | 181 .ack_reg = SRI(reg2, block, reg_num),\
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| /drivers/gpu/drm/amd/display/dc/irq/dcn20/ |
| A D | irq_service_dcn20.c | 184 .ack_reg = SRI(reg2, block, reg_num),\
|