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Searched refs:adjust (Results 1 – 25 of 89) sorted by relevance

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/drivers/gpu/drm/amd/display/modules/freesync/
A Dfreesync.c225 in_out_vrr->adjust.v_total_max); in update_v_total_for_static_ramp()
326 in_out_vrr->adjust.v_total_min = in apply_below_the_range()
329 in_out_vrr->adjust.v_total_max = in apply_below_the_range()
491 in_out_vrr->adjust.v_total_min = in apply_fixed_refresh()
494 in_out_vrr->adjust.v_total_max = in apply_fixed_refresh()
497 in_out_vrr->adjust.v_total_min = in apply_fixed_refresh()
500 in_out_vrr->adjust.v_total_max = in apply_fixed_refresh()
1097 in_out_vrr->adjust.v_total_min = in mod_freesync_build_vrr_params()
1100 in_out_vrr->adjust.v_total_max = in mod_freesync_build_vrr_params()
1195 in_out_vrr->adjust.v_total_min = in mod_freesync_handle_v_update()
[all …]
/drivers/gpu/drm/amd/display/modules/hdcp/
A Dhdcp.c43 hdcp->connection.link.adjust.hdcp1.disable = 1; in push_error_status()
47 hdcp->connection.link.adjust.hdcp2.disable = 1; in push_error_status()
67 !hdcp->connection.link.adjust.hdcp1.disable && in is_cp_desired_hdcp1()
262 display->adjust.disable == true && in update_display_adjustments()
264 display->adjust.disable = false; in update_display_adjustments()
271 display->adjust.disable = true; in update_display_adjustments()
275 memcmp(adj, &display->adjust, in update_display_adjustments()
443 memcmp(display_adjust, &display->adjust, in mod_hdcp_update_display()
451 memcmp(display_adjust, &display->adjust, in mod_hdcp_update_display()
470 hdcp->connection.link.adjust = *link_adjust; in mod_hdcp_update_display()
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A Dhdcp1_transition.c35 struct mod_hdcp_link_adjustment *adjust = &hdcp->connection.link.adjust; in mod_hdcp_hdcp1_transition() local
51 adjust->hdcp1.disable = 1; in mod_hdcp_hdcp1_transition()
111 adjust->hdcp1.postpone_encryption = 1; in mod_hdcp_hdcp1_transition()
158 struct mod_hdcp_link_adjustment *adjust = &hdcp->connection.link.adjust; in mod_hdcp_hdcp1_dp_transition() local
167 adjust->hdcp1.disable = 1; in mod_hdcp_hdcp1_dp_transition()
177 adjust->hdcp1.disable = 1; in mod_hdcp_hdcp1_dp_transition()
233 } else if (conn->hdcp1_retry_count < conn->link.adjust.hdcp1.min_auth_retries_wa) { in mod_hdcp_hdcp1_dp_transition()
263 adjust->hdcp1.postpone_encryption = 1; in mod_hdcp_hdcp1_dp_transition()
287 adjust->hdcp1.postpone_encryption = 1; in mod_hdcp_hdcp1_dp_transition()
A Dhdcp2_transition.c35 struct mod_hdcp_link_adjustment *adjust = &hdcp->connection.link.adjust; in mod_hdcp_hdcp2_transition() local
41 adjust->hdcp2.disable = 1; in mod_hdcp_hdcp2_transition()
53 adjust->hdcp2.disable = 1; in mod_hdcp_hdcp2_transition()
91 !adjust->hdcp2.force_no_stored_km) { in mod_hdcp_hdcp2_transition()
104 if (adjust->hdcp2.increase_h_prime_timeout) in mod_hdcp_hdcp2_transition()
180 adjust->hdcp2.force_no_stored_km = 1; in mod_hdcp_hdcp2_transition()
388 struct mod_hdcp_link_adjustment *adjust = &hdcp->connection.link.adjust; in mod_hdcp_hdcp2_dp_transition() local
394 adjust->hdcp2.disable = 1; in mod_hdcp_hdcp2_dp_transition()
406 adjust->hdcp2.disable = 1; in mod_hdcp_hdcp2_dp_transition()
428 !adjust->hdcp2.force_no_stored_km) { in mod_hdcp_hdcp2_dp_transition()
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/drivers/gpu/drm/tegra/
A Ddp.c375 struct drm_dp_link_train_set *adjust = &train->adjust; in drm_dp_link_train_init() local
380 adjust->voltage_swing[i] = 0; in drm_dp_link_train_init()
383 adjust->pre_emphasis[i] = 0; in drm_dp_link_train_init()
386 adjust->post_cursor[i] = 0; in drm_dp_link_train_init()
483 struct drm_dp_link_train_set *adjust = &link->train.adjust; in drm_dp_link_get_adjustments() local
496 adjust->voltage_swing[i] = in drm_dp_link_get_adjustments()
500 adjust->pre_emphasis[i] = in drm_dp_link_get_adjustments()
504 adjust->post_cursor[i] = in drm_dp_link_get_adjustments()
512 struct drm_dp_link_train_set *adjust = &train->adjust; in drm_dp_link_train_adjust() local
521 request->pre_emphasis[i] = adjust->pre_emphasis[i]; in drm_dp_link_train_adjust()
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/drivers/tty/
A Dtty_ldsem.c78 long adjust, count; in __ldsem_wake_readers() local
85 adjust = sem->wait_readers * (LDSEM_ACTIVE_BIAS - LDSEM_WAIT_BIAS); in __ldsem_wake_readers()
86 count = atomic_long_add_return(adjust, &sem->count); in __ldsem_wake_readers()
90 if (atomic_long_try_cmpxchg(&sem->count, &count, count - adjust)) in __ldsem_wake_readers()
159 long adjust = -LDSEM_ACTIVE_BIAS + LDSEM_WAIT_BIAS; in down_read_failed() local
170 if (atomic_long_try_cmpxchg(&sem->count, &count, count + adjust)) { in down_read_failed()
171 count += adjust; in down_read_failed()
233 long adjust = -LDSEM_ACTIVE_BIAS; in down_write_failed() local
245 if (atomic_long_try_cmpxchg(&sem->count, &count, count + adjust)) in down_write_failed()
/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
A Dgm20b.c66 gm20b_pmu_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) in gm20b_pmu_acr_bld_patch() argument
73 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
74 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
76 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
77 hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
79 hdr.overlay_dma_base = lower_32_bits((addr + adjust) << 8); in gm20b_pmu_acr_bld_patch()
80 hdr.overlay_dma_base1 = upper_32_bits((addr + adjust) << 8); in gm20b_pmu_acr_bld_patch()
/drivers/gpu/drm/nouveau/nvkm/engine/gr/
A Dgm20b.c34 gm20b_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) in gm20b_gr_acr_bld_patch() argument
41 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
42 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
44 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
45 hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
A Dgp108.c29 gp108_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) in gp108_gr_acr_bld_patch() argument
33 hdr.code_dma_base = hdr.code_dma_base + adjust; in gp108_gr_acr_bld_patch()
34 hdr.data_dma_base = hdr.data_dma_base + adjust; in gp108_gr_acr_bld_patch()
A Dgm200.c46 gm200_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) in gm200_gr_acr_bld_patch() argument
50 hdr.code_dma_base = hdr.code_dma_base + adjust; in gm200_gr_acr_bld_patch()
51 hdr.data_dma_base = hdr.data_dma_base + adjust; in gm200_gr_acr_bld_patch()
/drivers/gpu/drm/nouveau/nvkm/engine/sec2/
A Dgp102.c78 gp102_sec2_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) in gp102_sec2_acr_bld_patch() argument
82 hdr.code_dma_base = hdr.code_dma_base + adjust; in gp102_sec2_acr_bld_patch()
83 hdr.data_dma_base = hdr.data_dma_base + adjust; in gp102_sec2_acr_bld_patch()
84 hdr.overlay_dma_base = hdr.overlay_dma_base + adjust; in gp102_sec2_acr_bld_patch()
241 gp102_sec2_acr_bld_patch_1(struct nvkm_acr *acr, u32 bld, s64 adjust) in gp102_sec2_acr_bld_patch_1() argument
245 hdr.code_dma_base = hdr.code_dma_base + adjust; in gp102_sec2_acr_bld_patch_1()
246 hdr.data_dma_base = hdr.data_dma_base + adjust; in gp102_sec2_acr_bld_patch_1()
/drivers/gpu/drm/amd/display/dc/mpc/dcn401/
A Ddcn401_mpc.c421 const struct mpc_grph_gamut_adjustment *adjust) in mpc401_set_gamut_remap() argument
427 if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW) { in mpc401_set_gamut_remap()
430 adjust->mpcc_gamut_remap_block_id, MPCC_GAMUT_REMAP_MODE_SELECT_0); in mpc401_set_gamut_remap()
436 arr_matrix[i] = adjust->temperature_matrix[i]; in mpc401_set_gamut_remap()
440 switch (adjust->mpcc_gamut_remap_block_id) { in mpc401_set_gamut_remap()
464 adjust->mpcc_gamut_remap_block_id, mode_select); in mpc401_set_gamut_remap()
561 struct mpc_grph_gamut_adjustment *adjust) in mpc401_get_gamut_remap() argument
566 mpc_read_gamut_remap(mpc, mpcc_id, arr_reg_val, adjust->mpcc_gamut_remap_block_id, &mode_select); in mpc401_get_gamut_remap()
569 adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; in mpc401_get_gamut_remap()
573 adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; in mpc401_get_gamut_remap()
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/drivers/media/platform/samsung/exynos4-is/
A Dfimc-is-param.c99 __hw_param_copy(&par->isp.adjust, &cfg->isp.adjust); in __fimc_is_hw_update_param()
363 isp->adjust.contrast = val; in __is_set_isp_adjust()
372 isp->adjust.exposure = val; in __is_set_isp_adjust()
378 isp->adjust.hue = val; in __is_set_isp_adjust()
381 isp->adjust.contrast = 0; in __is_set_isp_adjust()
382 isp->adjust.saturation = 0; in __is_set_isp_adjust()
383 isp->adjust.sharpness = 0; in __is_set_isp_adjust()
384 isp->adjust.exposure = 0; in __is_set_isp_adjust()
386 isp->adjust.hue = 0; in __is_set_isp_adjust()
391 isp->adjust.cmd = cmd; in __is_set_isp_adjust()
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/drivers/iio/common/inv_sensors/
A Dinv_sensors_timestamp.c116 int64_t adjust; in inv_align_timestamp_it() local
126 adjust = add_max; in inv_align_timestamp_it()
128 adjust = sub_max; in inv_align_timestamp_it()
130 adjust = 0; in inv_align_timestamp_it()
132 ts->timestamp += adjust; in inv_align_timestamp_it()
/drivers/gpu/drm/amd/display/dc/hwss/dce60/
A Ddce60_hwseq.c275 struct xfm_grph_csc_adjustment adjust; in dce60_program_front_end_for_pipe() local
283 memset(&adjust, 0, sizeof(adjust)); in dce60_program_front_end_for_pipe()
284 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; in dce60_program_front_end_for_pipe()
303 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; in dce60_program_front_end_for_pipe()
306 adjust.temperature_matrix[i] = in dce60_program_front_end_for_pipe()
310 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); in dce60_program_front_end_for_pipe()
/drivers/ata/
A Dpata_hpt37x.c948 int dpll, adjust; in hpt37x_init_one() local
963 for (adjust = 0; adjust < 8; adjust++) { in hpt37x_init_one()
970 if (adjust & 1) in hpt37x_init_one()
971 f_low -= adjust >> 1; in hpt37x_init_one()
973 f_high += adjust >> 1; in hpt37x_init_one()
977 if (adjust == 8) { in hpt37x_init_one()
A Dpata_hpt3x2n.c496 int adjust; in hpt3x2n_init_one() local
575 for (adjust = 0; adjust < 8; adjust++) { in hpt3x2n_init_one()
580 if (adjust == 8) { in hpt3x2n_init_one()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
A Ddce110_clk_mgr.c102 struct dc_crtc_timing_adjust adjust = stream->adjust; in dce110_get_min_vblank_time_us() local
103 if (adjust.v_total_max != adjust.v_total_min) in dce110_get_min_vblank_time_us()
104 vertical_total_min = adjust.v_total_min; in dce110_get_min_vblank_time_us()
/drivers/net/ethernet/intel/igc/
A Digc_ptp.c463 int adjust; in igc_ptp_rx_pktstamp() local
473 adjust = IGC_I225_RX_LATENCY_10; in igc_ptp_rx_pktstamp()
476 adjust = IGC_I225_RX_LATENCY_100; in igc_ptp_rx_pktstamp()
479 adjust = IGC_I225_RX_LATENCY_1000; in igc_ptp_rx_pktstamp()
482 adjust = IGC_I225_RX_LATENCY_2500; in igc_ptp_rx_pktstamp()
485 adjust = 0; in igc_ptp_rx_pktstamp()
720 int adjust = 0; in igc_ptp_tx_reg_to_stamp() local
731 adjust = IGC_I225_TX_LATENCY_10; in igc_ptp_tx_reg_to_stamp()
734 adjust = IGC_I225_TX_LATENCY_100; in igc_ptp_tx_reg_to_stamp()
737 adjust = IGC_I225_TX_LATENCY_1000; in igc_ptp_tx_reg_to_stamp()
[all …]
/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
A Ddcn30_dpp_cm.c375 const struct dpp_grph_csc_adjustment *adjust) in dpp3_cm_set_gamut_remap() argument
381 if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW) in dpp3_cm_set_gamut_remap()
389 arr_matrix[i] = adjust->temperature_matrix[i]; in dpp3_cm_set_gamut_remap()
445 struct dpp_grph_csc_adjustment *adjust) in dpp3_cm_get_gamut_remap() argument
454 adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; in dpp3_cm_get_gamut_remap()
458 adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; in dpp3_cm_get_gamut_remap()
459 convert_hw_matrix(adjust->temperature_matrix, in dpp3_cm_get_gamut_remap()
/drivers/gpu/drm/amd/display/dc/dwb/dcn30/
A Ddcn30_dwb_cm.c360 struct cm_grph_csc_adjustment adjust = params->csc_params; in dwb3_set_gamut_remap() local
363 if (adjust.gamut_adjust_type != CM_GAMUT_ADJUST_TYPE_SW) { in dwb3_set_gamut_remap()
365 dwb3_program_gamut_remap(dwbc, NULL, adjust.gamut_coef_format, CM_GAMUT_REMAP_MODE_BYPASS); in dwb3_set_gamut_remap()
372 arr_matrix[i] = adjust.temperature_matrix[i]; in dwb3_set_gamut_remap()
380 adjust.gamut_coef_format, CM_GAMUT_REMAP_MODE_RAMB_COEFF); in dwb3_set_gamut_remap()
383 adjust.gamut_coef_format, CM_GAMUT_REMAP_MODE_RAMA_COEFF); in dwb3_set_gamut_remap()
/drivers/media/tuners/
A Dtda9887.c311 static char *adjust[32] = { in dump_write_message() local
361 adjust[buf[2] & 0x1f]); in dump_write_message()
436 static unsigned int adjust = UNSET; variable
441 module_param(adjust, int, 0644);
468 if (adjust < 0x20) { in tda9887_set_insmod()
470 buf[2] |= adjust; in tda9887_set_insmod()
/drivers/net/ethernet/intel/igb/
A Digb_ptp.c945 int adjust = 0; in igb_ptp_tx_hwtstamp() local
955 adjust = IGB_I210_TX_LATENCY_10; in igb_ptp_tx_hwtstamp()
958 adjust = IGB_I210_TX_LATENCY_100; in igb_ptp_tx_hwtstamp()
961 adjust = IGB_I210_TX_LATENCY_1000; in igb_ptp_tx_hwtstamp()
1001 int adjust = 0; in igb_ptp_rx_pktstamp() local
1021 adjust = IGB_I210_RX_LATENCY_10; in igb_ptp_rx_pktstamp()
1024 adjust = IGB_I210_RX_LATENCY_100; in igb_ptp_rx_pktstamp()
1027 adjust = IGB_I210_RX_LATENCY_1000; in igb_ptp_rx_pktstamp()
1049 int adjust = 0; in igb_ptp_rx_rgtstamp() local
1077 adjust = IGB_I210_RX_LATENCY_10; in igb_ptp_rx_rgtstamp()
[all …]
/drivers/mmc/host/
A Dmeson-gx-mmc.c140 unsigned int adjust; member
509 unsigned int val = readl(host->regs + host->data->adjust); in meson_mmc_disable_resampling()
512 writel(val, host->regs + host->data->adjust); in meson_mmc_disable_resampling()
521 val = readl(host->regs + host->data->adjust); in meson_mmc_reset_resampling()
523 writel(val, host->regs + host->data->adjust); in meson_mmc_reset_resampling()
536 val = readl(host->regs + host->data->adjust); in meson_mmc_resampling_tuning()
538 writel(val, host->regs + host->data->adjust); in meson_mmc_resampling_tuning()
548 writel(val, host->regs + host->data->adjust); in meson_mmc_resampling_tuning()
1313 .adjust = SD_EMMC_ADJUST,
1321 .adjust = SD_EMMC_V3_ADJUST,
/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
A Ddcn10_dpp_cm.c162 const struct dpp_grph_csc_adjustment *adjust) in dpp1_cm_set_gamut_remap() argument
167 if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW) in dpp1_cm_set_gamut_remap()
175 arr_matrix[i] = adjust->temperature_matrix[i]; in dpp1_cm_set_gamut_remap()
234 struct dpp_grph_csc_adjustment *adjust) in dpp1_cm_get_gamut_remap() argument
243 adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; in dpp1_cm_get_gamut_remap()
247 adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; in dpp1_cm_get_gamut_remap()
248 convert_hw_matrix(adjust->temperature_matrix, in dpp1_cm_get_gamut_remap()

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