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Searched refs:ae (Results 1 – 25 of 43) sorted by relevance

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/drivers/crypto/intel/qat/qat_common/
A Dqat_hal.c36 #define AE(handle, ae) ((handle)->hal_handle->aes[ae]) argument
382 unsigned char ae; in qat_hal_check_ae_alive() local
421 unsigned char ae; in qat_hal_reset_timestamp() local
479 unsigned char ae = 0; in qat_hal_clr_reset() local
608 unsigned char ae; in qat_hal_clear_xfer() local
624 unsigned char ae; in qat_hal_clear_gpr() local
692 unsigned char ae = 0; in qat_hal_chip_init() local
816 max_en_ae_id = ae; in qat_hal_chip_init()
898 unsigned char ae; in qat_hal_start() local
1290 unsigned char ae, in qat_hal_batch_wr_lm() argument
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A Dicp_qat_hal.h129 #define AE_CSR(handle, ae) \ argument
130 ((char __iomem *)(handle)->hal_cap_ae_local_csr_addr_v + ((ae) << 12))
131 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & (csr))) argument
132 #define SET_AE_CSR(handle, ae, csr, val) \ argument
133 ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
134 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0) argument
135 #define AE_XFER(handle, ae) \ argument
136 ((char __iomem *)(handle)->hal_cap_ae_xfer_csr_addr_v + ((ae) << 12))
137 #define AE_XFER_ADDR(handle, ae, reg) (AE_XFER(handle, ae) + \ argument
139 #define SET_AE_XFER(handle, ae, reg, val) \ argument
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A Dqat_uclo.c175 ae = umem_init->ae; in qat_uclo_batch_wr_umem()
204 unsigned long ae = 0; in qat_uclo_parse_num() local
284 mem_init->ae = ae; in qat_uclo_create_batch_init_list()
315 unsigned int ae; in qat_uclo_init_lmem_seg() local
374 unsigned char ae; in qat_uclo_init_ustore() local
416 int i, ae; in qat_uclo_init_memory() local
661 int i, ae; in qat_uclo_map_ae() local
870 unsigned int s, ae; in qat_uclo_init_globals() local
992 unsigned int ae; in qat_uclo_parse_uof_obj() local
1032 for (ae = 0; ae < obj_handle->uimage_num; ae++) in qat_uclo_parse_uof_obj()
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A Dadf_common_drv.h139 unsigned char ae, unsigned int ctx_mask);
141 unsigned int ae);
146 unsigned char ae, unsigned char mode);
148 unsigned char ae, unsigned char mode);
152 unsigned char ae, unsigned int uaddr,
159 unsigned char ae,
162 unsigned char ae, unsigned long ctx_mask,
166 unsigned char ae, unsigned long ctx_mask,
170 unsigned char ae, unsigned long ctx_mask,
174 unsigned char ae, unsigned long ctx_mask,
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A Dadf_fw_counters.c32 u16 ae; member
41 static void adf_fw_counters_parse_ae_values(struct adf_ae_counters *ae_counters, u32 ae, in adf_fw_counters_parse_ae_values() argument
44 ae_counters->ae = ae; in adf_fw_counters_parse_ae_values()
55 unsigned long ae; in adf_fw_counters_load_from_device() local
64 for_each_set_bit(ae, &ae_mask, GET_MAX_ACCELENGINES(accel_dev)) { in adf_fw_counters_load_from_device()
68 ret = adf_get_ae_fw_counters(accel_dev, ae, &req_count, &resp_count); in adf_fw_counters_load_from_device()
72 adf_fw_counters_parse_ae_values(&fw_counters->ae_counters[i++], ae, in adf_fw_counters_load_from_device()
176 seq_printf(sfile, "%2d:", ae_counters->ae); in qat_fw_counters_seq_show()
A Dadf_admin.c119 int offset = ae * ADF_ADMINMSG_LEN * 2; in adf_put_admin_msg_sync()
121 int mb_offset = ae * ADF_ADMIN_MAILBOX_STRIDE; in adf_put_admin_msg_sync()
142 request->cmd_id, ae); in adf_put_admin_msg_sync()
160 u32 ae; in adf_send_admin() local
162 for_each_set_bit(ae, &ae_mask, ICP_QAT_HW_AE_DELIMITER) in adf_send_admin()
163 if (adf_put_admin_msg_sync(accel_dev, ae, req, resp) || in adf_send_admin()
235 unsigned long ae; in adf_get_dc_capabilities() local
246 for_each_set_bit(ae, &ae_mask, GET_MAX_ACCELENGINES(accel_dev)) { in adf_get_dc_capabilities()
247 ret = adf_send_admin(accel_dev, &req, &resp, 1ULL << ae); in adf_get_dc_capabilities()
265 ret = adf_put_admin_msg_sync(accel_dev, ae, &req, &resp); in adf_get_ae_fw_counters()
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A Dadf_cnv_dbgfs.c67 u16 ae; member
143 seq_printf(sfile, "%d:", ae_errors->ae); in qat_cnv_errors_seq_show()
179 unsigned long ae; in cnv_err_stats_alloc() local
204 for_each_set_bit(ae, &ae_mask, GET_MAX_ACCELENGINES(accel_dev)) { in cnv_err_stats_alloc()
205 ret = adf_get_cnv_stats(accel_dev, ae, &err_cnt, &latest_err); in cnv_err_stats_alloc()
209 ae, ret); in cnv_err_stats_alloc()
216 err_stats->ae_cnv_errors[i].ae = ae; in cnv_err_stats_alloc()
A Dadf_accel_engine.c145 u32 ae_ctr, ae, max_aes = GET_MAX_ACCELENGINES(accel_dev); in adf_ae_stop() local
150 for (ae = 0, ae_ctr = 0; ae < max_aes; ae++) { in adf_ae_stop()
151 if (hw_data->ae_mask & (1 << ae)) { in adf_ae_stop()
152 qat_hal_stop(loader_data->fw_loader, ae, 0xFF); in adf_ae_stop()
162 static int adf_ae_reset(struct adf_accel_dev *accel_dev, int ae) in adf_ae_reset() argument
A Dadf_gen6_ras.c204 u32 ae, errsou; in adf_gen6_process_errsou0() local
206 ae = ADF_CSR_RD(csr, ADF_GEN6_HIAECORERRLOG_CPP0); in adf_gen6_process_errsou0()
207 ae &= GET_HW_DATA(accel_dev)->ae_mask; in adf_gen6_process_errsou0()
209 dev_warn(&GET_DEV(accel_dev), "Correctable error detected: %#x\n", ae); in adf_gen6_process_errsou0()
214 ADF_CSR_WR(csr, ADF_GEN6_HIAECORERRLOG_CPP0, ae); in adf_gen6_process_errsou0()
224 u32 ae; in adf_handle_cpp_ae_unc() local
229 ae = ADF_CSR_RD(csr, ADF_GEN6_HIAEUNCERRLOG_CPP0); in adf_handle_cpp_ae_unc()
230 ae &= GET_HW_DATA(accel_dev)->ae_mask; in adf_handle_cpp_ae_unc()
231 if (ae) { in adf_handle_cpp_ae_unc()
232 dev_err(&GET_DEV(accel_dev), "Uncorrectable error detected: %#x\n", ae); in adf_handle_cpp_ae_unc()
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A Dadf_hw_arbiter.c103 int adf_disable_arb_thd(struct adf_accel_dev *accel_dev, u32 ae, u32 thr) in adf_disable_arb_thd() argument
120 ae_thr_map = *(thd_2_arb_cfg + ae); in adf_disable_arb_thd()
123 WRITE_CSR_ARB_WT2SAM(csr, info.arb_offset, info.wt2sam_offset, ae, in adf_disable_arb_thd()
A Dadf_admin.h13 int adf_get_ae_fw_counters(struct adf_accel_dev *accel_dev, u16 ae, u64 *reqs, u64 *resps);
25 int adf_get_cnv_stats(struct adf_accel_dev *accel_dev, u16 ae, u16 *err_cnt, u16 *latest_err);
A Dadf_heartbeat_inject.c23 static void adf_set_hb_counters_fail(struct adf_accel_dev *accel_dev, u32 ae, in adf_set_hb_counters_fail() argument
30 size_t thr_id = ae * hb_ctrs + thr; in adf_set_hb_counters_fail()
A Dadf_heartbeat.c171 size_t ae = 0; in adf_hb_get_status() local
190 for_each_set_bit(ae, &ae_mask, max_aes) { in adf_hb_get_status()
191 ae_offset = size_mul(ae, hb_ctrs); in adf_hb_get_status()
/drivers/scsi/esas2r/
A Desas2r_int.c723 switch (ae->lu.bystate) { in esas2r_lun_event()
751 union atto_vda_ae *ae = in esas2r_ae_complete() local
771 last = ae; in esas2r_ae_complete()
774 while (ae < last) { in esas2r_ae_complete()
787 ae, length); in esas2r_ae_complete()
795 esas2r_nuxi_ae_data(ae); in esas2r_ae_complete()
809 ae->raid.acname, in esas2r_ae_complete()
819 ae->lu.dwevent, in esas2r_ae_complete()
822 ae->lu.bystate); in esas2r_ae_complete()
844 ae = (union atto_vda_ae *)((u8 *)ae + length); in esas2r_ae_complete()
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A Desas2r_main.c1451 void esas2r_nuxi_ae_data(union atto_vda_ae *ae) in esas2r_nuxi_ae_data() argument
1453 struct atto_vda_ae_raid *r = &ae->raid; in esas2r_nuxi_ae_data()
1454 struct atto_vda_ae_lu *l = &ae->lu; in esas2r_nuxi_ae_data()
1456 switch (ae->hdr.bytype) { in esas2r_nuxi_ae_data()
1712 switch (ae->vda_ae.hdr.bytype) { in esas2r_send_ae_event()
1782 ae->vda_ae.hdr.bylength); in esas2r_send_ae_event()
1841 struct esas2r_vda_ae *ae = in esas2r_queue_fw_event() local
1844 ae->signature = ESAS2R_VDA_EVENT_SIG; in esas2r_queue_fw_event()
1845 ae->bus_number = a->pcid->bus->number; in esas2r_queue_fw_event()
1846 ae->devfn = a->pcid->devfn; in esas2r_queue_fw_event()
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/drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/
A Dia_css_s3a.host.c97 ia_css_ae_encode(&to->ae, from, sizeof(to->ae)); in ia_css_s3a_encode()
132 const struct sh_css_isp_ae_params *ae, in ia_css_ae_dump() argument
135 if (!ae) return; in ia_css_ae_dump()
137 "ae_y_coef_r", ae->y_coef_r); in ia_css_ae_dump()
139 "ae_y_coef_g", ae->y_coef_g); in ia_css_ae_dump()
141 "ae_y_coef_b", ae->y_coef_b); in ia_css_ae_dump()
198 ia_css_ae_dump(&s3a->ae, level); in ia_css_s3a_dump()
A Dia_css_s3a_param.h36 struct sh_css_isp_ae_params ae; member
A Dia_css_s3a.host.h29 const struct sh_css_isp_ae_params *ae,
/drivers/staging/media/ipu3/
A Dipu3-css-params.c2445 acc->ae.grid_cfg = acc_user->ae.grid_cfg; in imgu_css_cfg_acc()
2446 acc->ae.ae_ccm = acc_user->ae.ae_ccm; in imgu_css_cfg_acc()
2448 acc->ae.weights[i] = acc_user->ae.weights[i]; in imgu_css_cfg_acc()
2451 acc->ae.grid_cfg = acc_old->ae.grid_cfg; in imgu_css_cfg_acc()
2452 acc->ae.ae_ccm = acc_old->ae.ae_ccm; in imgu_css_cfg_acc()
2454 acc->ae.weights[i] = acc_old->ae.weights[i]; in imgu_css_cfg_acc()
2467 acc->ae.grid_cfg.x_end = imgu_css_grid_end(acc->ae.grid_cfg.x_start, in imgu_css_cfg_acc()
2468 acc->ae.grid_cfg.width, in imgu_css_cfg_acc()
2471 acc->ae.grid_cfg.y_end = imgu_css_grid_end(acc->ae.grid_cfg.y_start, in imgu_css_cfg_acc()
2476 acc->ae.stripes[i].grid = acc->ae.grid_cfg; in imgu_css_cfg_acc()
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/drivers/media/platform/rockchip/rkisp1/
A Drkisp1-stats.c225 pbuf->params.ae.exp_mean[i] = in rkisp1_stats_get_aec_meas_v10()
240 pbuf->params.ae.exp_mean[4 * i + 0] = in rkisp1_stats_get_aec_meas_v12()
242 pbuf->params.ae.exp_mean[4 * i + 1] = in rkisp1_stats_get_aec_meas_v12()
244 pbuf->params.ae.exp_mean[4 * i + 2] = in rkisp1_stats_get_aec_meas_v12()
246 pbuf->params.ae.exp_mean[4 * i + 3] = in rkisp1_stats_get_aec_meas_v12()
251 pbuf->params.ae.exp_mean[4 * i + 0] = RKISP1_CIF_ISP_EXP_GET_MEAN_xy0_V12(value); in rkisp1_stats_get_aec_meas_v12()
318 bls_val = &pbuf->params.ae.bls_val; in rkisp1_stats_get_bls_meas()
/drivers/scsi/lpfc/
A Dlpfc_ct.c2493 int size = sizeof(*ae); in lpfc_fdmi_set_attr_u32()
2496 ae->len = cpu_to_be16(size); in lpfc_fdmi_set_attr_u32()
2506 int size = sizeof(*ae); in lpfc_fdmi_set_attr_wwn()
2509 ae->len = cpu_to_be16(size); in lpfc_fdmi_set_attr_wwn()
2511 memcpy(ae->name, wwn, in lpfc_fdmi_set_attr_wwn()
2522 u8 *nname = ae->nname; in lpfc_fdmi_set_attr_fullwwn()
2523 u8 *pname = ae->pname; in lpfc_fdmi_set_attr_fullwwn()
2524 int size = sizeof(*ae); in lpfc_fdmi_set_attr_fullwwn()
2549 strscpy(ae->value_string, attrstring, sizeof(ae->value_string)); in lpfc_fdmi_set_attr_string()
2550 len = strnlen(ae->value_string, sizeof(ae->value_string)); in lpfc_fdmi_set_attr_string()
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/drivers/crypto/cavium/cpt/
A Dcpt_hw_types.h195 u64 ae:8; member
201 u64 ae:8;
/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
A Ddma.c727 u32 ae; in dma64_dd_upd() local
729 ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT; in dma64_dd_upd()
732 ctrl2 |= (ae << D64_CTRL2_AE_SHIFT) & D64_CTRL2_AE; in dma64_dd_upd()
797 u32 ae; in _dma_ddtable_init() local
800 ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT; in _dma_ddtable_init()
809 D64_XC_AE, (ae << D64_XC_AE_SHIFT)); in _dma_ddtable_init()
816 D64_RC_AE, (ae << D64_RC_AE_SHIFT)); in _dma_ddtable_init()
/drivers/crypto/marvell/octeontx/
A Dotx_cpt_hw_types.h333 u64 ae:8; member
339 u64 ae:8;
/drivers/power/supply/
A Dbq27xxx_battery.c1688 int ae; local
1690 ae = bq27xxx_read(di, BQ27XXX_REG_AE, false);
1691 if (ae < 0) {
1693 return ae;
1697 ae *= BQ27XXX_POWER_CONSTANT / BQ27XXX_RS;
1699 ae *= 1000;
1701 val->intval = ae;

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