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Searched refs:amdgpu_gfx_create_bitmask (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_gfx.h563 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width) in amdgpu_gfx_create_bitmask() function
A Dgfxhub_v2_1.c514 u32 max_sa_mask = amdgpu_gfx_create_bitmask( in gfxhub_v2_1_utcl2_harvest()
A Dgfx_v12_0.c1701 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v12_0_get_sa_active_bitmap()
1720 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * in gfx_v12_0_get_rb_active_bitmap()
1746 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa); in gfx_v12_0_setup_rb()
5701 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); in gfx_v12_0_get_wgp_active_bitmap_per_sh()
A Dgfx_v6_0.c1338 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/ in gfx_v6_0_get_rb_active_bitmap()
1541 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v6_0_get_cu_enabled()
A Dgfx_v11_0.c1970 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v11_0_get_sa_active_bitmap()
1989 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * in gfx_v11_0_get_rb_active_bitmap()
2015 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa); in gfx_v11_0_setup_rb()
7429 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); in gfx_v11_0_get_wgp_active_bitmap_per_sh()
A Dgfx_v7_0.c1602 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v7_0_get_rb_active_bitmap()
3749 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v7_0_get_cu_active_bitmap()
A Dgfx_v10_0.c5093 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v10_0_get_rb_active_bitmap()
5266 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( in gfx_v10_0_tcp_harvest()
5275 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( in gfx_v10_0_tcp_harvest()
10083 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); in gfx_v10_0_get_wgp_active_bitmap_per_sh()
10190 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v10_3_get_disabled_sa()
A Dgfx_v8_0.c3422 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v8_0_get_rb_active_bitmap()
7036 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v8_0_get_cu_active_bitmap()
A Dgfx_v9_0.c2532 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v9_0_get_rb_active_bitmap()
7752 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v9_0_get_cu_active_bitmap()
A Dgfx_v9_4_3.c4885 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v9_4_3_get_cu_active_bitmap()

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