| /drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_hdp.c | 62 amdgpu_ring_emit_wreg(ring, in amdgpu_hdp_generic_flush()
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| A D | gmc_v11_0.c | 361 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + in gmc_v11_0_emit_flush_gpu_tlb()
365 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + in gmc_v11_0_emit_flush_gpu_tlb()
381 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + in gmc_v11_0_emit_flush_gpu_tlb()
398 amdgpu_ring_emit_wreg(ring, reg, pasid); in gmc_v11_0_emit_pasid_mapping()
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| A D | gmc_v12_0.c | 381 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + in gmc_v12_0_emit_flush_gpu_tlb()
385 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + in gmc_v12_0_emit_flush_gpu_tlb()
401 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + in gmc_v12_0_emit_flush_gpu_tlb()
418 amdgpu_ring_emit_wreg(ring, reg, pasid); in gmc_v12_0_emit_pasid_mapping()
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| A D | gmc_v10_0.c | 396 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + in gmc_v10_0_emit_flush_gpu_tlb()
400 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + in gmc_v10_0_emit_flush_gpu_tlb()
416 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + in gmc_v10_0_emit_flush_gpu_tlb()
433 amdgpu_ring_emit_wreg(ring, reg, pasid); in gmc_v10_0_emit_pasid_mapping()
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| A D | hdp_v4_0.c | 51 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( in hdp_v4_0_invalidate_hdp()
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| A D | hdp_v5_2.c | 48 amdgpu_ring_emit_wreg(ring, in hdp_v5_2_flush_hdp()
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| A D | hdp_v5_0.c | 37 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( in hdp_v5_0_invalidate_hdp()
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| A D | gmc_v9_0.c | 1000 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + in gmc_v9_0_emit_flush_gpu_tlb()
1004 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + in gmc_v9_0_emit_flush_gpu_tlb()
1020 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + in gmc_v9_0_emit_flush_gpu_tlb()
1041 amdgpu_ring_emit_wreg(ring, reg, pasid); in gmc_v9_0_emit_pasid_mapping()
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| A D | gmc_v7_0.c | 486 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); in gmc_v7_0_emit_flush_gpu_tlb()
489 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); in gmc_v7_0_emit_flush_gpu_tlb()
497 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); in gmc_v7_0_emit_pasid_mapping()
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| A D | gmc_v6_0.c | 370 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); in gmc_v6_0_emit_flush_gpu_tlb()
373 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); in gmc_v6_0_emit_flush_gpu_tlb()
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| A D | gmc_v8_0.c | 677 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); in gmc_v8_0_emit_flush_gpu_tlb()
680 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); in gmc_v8_0_emit_flush_gpu_tlb()
688 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); in gmc_v8_0_emit_pasid_mapping()
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| A D | sdma_v6_0.c | 1201 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + in sdma_v6_0_ring_emit_vm_flush()
1204 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + in sdma_v6_0_ring_emit_vm_flush()
1248 amdgpu_ring_emit_wreg(ring, reg0, ref); in sdma_v6_0_ring_emit_reg_write_reg_wait()
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| A D | sdma_v5_2.c | 1198 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + in sdma_v5_2_ring_emit_vm_flush()
1201 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + in sdma_v5_2_ring_emit_vm_flush()
1245 amdgpu_ring_emit_wreg(ring, reg0, ref); in sdma_v5_2_ring_emit_reg_write_reg_wait()
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| A D | cik.c | 1864 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); in cik_flush_hdp()
1875 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); in cik_invalidate_hdp()
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| A D | amdgpu_ring.h | 430 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) macro
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| A D | amdgpu_ring.c | 444 amdgpu_ring_emit_wreg(ring, reg0, ref); in amdgpu_ring_emit_reg_write_reg_wait_helper()
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| A D | vi.c | 1317 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); in vi_flush_hdp()
1328 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); in vi_invalidate_hdp()
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| A D | si.c | 1504 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); in si_flush_hdp()
1515 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); in si_invalidate_hdp()
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| A D | sdma_v7_0.c | 1250 amdgpu_ring_emit_wreg(ring, reg0, ref); in sdma_v7_0_ring_emit_reg_write_reg_wait()
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| A D | sdma_v5_0.c | 1324 amdgpu_ring_emit_wreg(ring, reg0, ref); in sdma_v5_0_ring_emit_reg_write_reg_wait()
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| A D | amdgpu_gfx.c | 1151 amdgpu_ring_emit_wreg(ring, reg, v); in amdgpu_kiq_wreg()
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| A D | gfx_v9_0.c | 5751 amdgpu_ring_emit_wreg(ring, in gfx_v9_0_ring_preempt_ib()
7130 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); in gfx_v9_0_emit_wave_limit_cs()
7145 amdgpu_ring_emit_wreg(ring, in gfx_v9_0_emit_wave_limit()
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| A D | gfx_v9_4_3.c | 3438 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); in gfx_v9_4_3_emit_wave_limit_cs()
3452 amdgpu_ring_emit_wreg(ring, in gfx_v9_4_3_emit_wave_limit()
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| A D | gfx_v8_0.c | 6788 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); in gfx_v8_0_emit_wave_limit_cs()
6804 amdgpu_ring_emit_wreg(ring, mmSPI_WCL_PIPE_PERCENT_GFX, val); in gfx_v8_0_emit_wave_limit()
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| A D | gfx_v12_0.c | 3980 amdgpu_ring_emit_wreg(ring, reg, data); in gfx_v12_0_update_spm_vmid()
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