Searched refs:apb_base (Results 1 – 8 of 8) sorted by relevance
| /drivers/pci/controller/dwc/ |
| A D | pcie-keembay.c | 60 void __iomem *apb_base; member
96 val = readl(pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set()
101 writel(val, pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set()
216 writel(val, pcie->apb_base + PCIE_REGS_LJPLL_CNTRL_2); in keembay_pcie_pll_init()
220 writel(val, pcie->apb_base + PCIE_REGS_LJPLL_CNTRL_3); in keembay_pcie_pll_init()
223 writel(val, pcie->apb_base + PCIE_REGS_LJPLL_CNTRL_0); in keembay_pcie_pll_init()
363 val = readl(pcie->apb_base + PCIE_REGS_PCIE_PHY_CNTL); in keembay_pcie_add_pcie_port()
365 writel(val, pcie->apb_base + PCIE_REGS_PCIE_PHY_CNTL); in keembay_pcie_add_pcie_port()
373 val = readl(pcie->apb_base + PCIE_REGS_PCIE_CFG); in keembay_pcie_add_pcie_port()
418 if (IS_ERR(pcie->apb_base)) in keembay_pcie_probe()
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| A D | pcie-dw-rockchip.c | 73 void __iomem *apb_base; member
91 return readl_relaxed(rockchip->apb_base + reg); in rockchip_pcie_readl_apb()
97 writel_relaxed(val, rockchip->apb_base + reg); in rockchip_pcie_writel_apb()
395 rockchip->apb_base = devm_platform_ioremap_resource_byname(pdev, "apb"); in rockchip_pcie_resource_get()
396 if (IS_ERR(rockchip->apb_base)) in rockchip_pcie_resource_get()
397 return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->apb_base), in rockchip_pcie_resource_get()
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| A D | pcie-kirin.c | 453 void __iomem *apb_base; in kirin_pcie_get_resource() local
456 apb_base = devm_platform_ioremap_resource_byname(pdev, "apb"); in kirin_pcie_get_resource()
457 if (IS_ERR(apb_base)) in kirin_pcie_get_resource()
458 return PTR_ERR(apb_base); in kirin_pcie_get_resource()
460 kirin_pcie->apb = devm_regmap_init_mmio(dev, apb_base, in kirin_pcie_get_resource()
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| /drivers/net/ethernet/stmicro/stmmac/ |
| A D | dwmac-thead.c | 50 void __iomem *apb_base; member
75 writel(phyif, dwmac->apb_base + GMAC_INTF_CTRL); in thead_dwmac_set_phy_if()
100 writel(txclk_dir, dwmac->apb_base + GMAC_TXCLK_OEN); in thead_dwmac_set_txclk_dir()
126 writel(0, dwmac->apb_base + GMAC_PLLCLK_DIV); in thead_set_clk_tx_rate()
142 writel(reg, dwmac->apb_base + GMAC_PLLCLK_DIV); in thead_set_clk_tx_rate()
178 writel(reg, dwmac->apb_base + GMAC_CLK_EN); in thead_dwmac_enable_clk()
196 reg = readl(dwmac->apb_base + GMAC_RXCLK_DELAY_CTRL); in thead_dwmac_init()
199 writel(reg, dwmac->apb_base + GMAC_RXCLK_DELAY_CTRL); in thead_dwmac_init()
201 reg = readl(dwmac->apb_base + GMAC_TXCLK_DELAY_CTRL); in thead_dwmac_init()
204 writel(reg, dwmac->apb_base + GMAC_TXCLK_DELAY_CTRL); in thead_dwmac_init()
[all …]
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| /drivers/pci/controller/ |
| A D | pcie-rockchip.c | 50 rockchip->apb_base = in rockchip_pcie_parse_dt()
52 if (IS_ERR(rockchip->apb_base)) in rockchip_pcie_parse_dt()
53 return PTR_ERR(rockchip->apb_base); in rockchip_pcie_parse_dt()
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| A D | pcie-rockchip.h | 308 void __iomem *apb_base; /* DT apb-base */ member
334 return readl(rockchip->apb_base + reg); in rockchip_pcie_read()
340 writel(val, rockchip->apb_base + reg); in rockchip_pcie_write()
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| A D | pcie-rockchip-host.c | 97 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + where; in rockchip_pcie_rd_own_conf()
124 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + offset; in rockchip_pcie_wr_own_conf()
323 err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1, in rockchip_pcie_host_init_port()
344 err = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL, in rockchip_pcie_host_init_port()
852 err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_DEBUG_OUT_0, in rockchip_pcie_wait_l2()
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| A D | pcie-rockchip-ep.c | 543 ret = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL, in rockchip_pcie_ep_link_training()
550 ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1, in rockchip_pcie_ep_link_training()
564 readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL, in rockchip_pcie_ep_link_training()
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Completed in 22 milliseconds