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Searched refs:base_address (Results 1 – 25 of 69) sorted by relevance

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/drivers/char/xilinx_hwicap/
A Dbuffer_icap.c104 return in_be32(base_address + (offset << 2)); in buffer_icap_get_bram()
177 out_be32(base_address + (offset << 2), data); in buffer_icap_set_bram()
192 void __iomem *base_address = drvdata->base_address; in buffer_icap_device_read() local
194 if (buffer_icap_busy(base_address)) in buffer_icap_device_read()
202 buffer_icap_set_offset(base_address, offset); in buffer_icap_device_read()
205 while (buffer_icap_busy(base_address)) { in buffer_icap_device_read()
226 void __iomem *base_address = drvdata->base_address; in buffer_icap_device_write() local
228 if (buffer_icap_busy(base_address)) in buffer_icap_device_write()
239 while (buffer_icap_busy(base_address)) { in buffer_icap_device_write()
274 void __iomem *base_address = drvdata->base_address; in buffer_icap_set_configuration() local
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A Dfifo_icap.c97 out_be32(drvdata->base_address + XHI_WF_OFFSET, data); in fifo_icap_fifo_write()
108 u32 data = in_be32(drvdata->base_address + XHI_RF_OFFSET); in fifo_icap_fifo_read()
121 out_be32(drvdata->base_address + XHI_SZ_OFFSET, data); in fifo_icap_set_read_size()
186 return in_be32(drvdata->base_address + XHI_WFV_OFFSET); in fifo_icap_write_fifo_vacancy()
198 return in_be32(drvdata->base_address + XHI_RFO_OFFSET); in fifo_icap_read_fifo_occupancy()
364 reg_data = in_be32(drvdata->base_address + XHI_CR_OFFSET); in fifo_icap_reset()
366 out_be32(drvdata->base_address + XHI_CR_OFFSET, in fifo_icap_reset()
369 out_be32(drvdata->base_address + XHI_CR_OFFSET, in fifo_icap_reset()
385 reg_data = in_be32(drvdata->base_address + XHI_CR_OFFSET); in fifo_icap_flush_fifo()
387 out_be32(drvdata->base_address + XHI_CR_OFFSET, in fifo_icap_flush_fifo()
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A Dxilinx_hwicap.c641 drvdata->base_address = devm_platform_ioremap_resource(pdev, 0); in hwicap_setup()
642 if (IS_ERR(drvdata->base_address)) { in hwicap_setup()
643 retval = PTR_ERR(drvdata->base_address); in hwicap_setup()
/drivers/misc/ibmasm/
A Dlowlevel.h53 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; in ibmasm_enable_interrupts()
59 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; in ibmasm_disable_interrupts()
65 ibmasm_enable_interrupts(base_address, SP_INTR_MASK); in enable_sp_interrupts()
70 ibmasm_disable_interrupts(base_address, SP_INTR_MASK); in disable_sp_interrupts()
75 ibmasm_enable_interrupts(base_address, UART_INTR_MASK); in enable_uart_interrupts()
80 ibmasm_disable_interrupts(base_address, UART_INTR_MASK); in disable_uart_interrupts()
91 mfa = readl(base_address + OUTBOUND_QUEUE_PORT); in get_mfa_outbound()
100 writel(mfa, base_address + OUTBOUND_QUEUE_PORT); in set_mfa_outbound()
103 static inline u32 get_mfa_inbound(void __iomem *base_address) in get_mfa_inbound() argument
105 u32 mfa = readl(base_address + INBOUND_QUEUE_PORT); in get_mfa_inbound()
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A Dlowlevel.c26 mfa = get_mfa_inbound(sp->base_address); in ibmasm_send_i2o_message()
33 message = get_i2o_message(sp->base_address, mfa); in ibmasm_send_i2o_message()
38 set_mfa_inbound(sp->base_address, mfa); in ibmasm_send_i2o_message()
47 void __iomem *base_address = sp->base_address; in ibmasm_interrupt_handler() local
50 if (!sp_interrupt_pending(base_address)) in ibmasm_interrupt_handler()
60 mfa = get_mfa_outbound(base_address); in ibmasm_interrupt_handler()
62 struct i2o_message *msg = get_i2o_message(base_address, mfa); in ibmasm_interrupt_handler()
67 set_mfa_outbound(base_address, mfa); in ibmasm_interrupt_handler()
A Dmodule.c96 sp->base_address = pci_ioremap_bar(pdev, 0); in ibmasm_init_one()
97 if (!sp->base_address) { in ibmasm_init_one()
109 enable_sp_interrupts(sp->base_address); in ibmasm_init_one()
136 disable_sp_interrupts(sp->base_address); in ibmasm_init_one()
139 iounmap(sp->base_address); in ibmasm_init_one()
166 disable_sp_interrupts(sp->base_address); in ibmasm_remove_one()
171 iounmap(sp->base_address); in ibmasm_remove_one()
A Duart.c25 iomem_base = sp->base_address + SCOUT_COM_B_BASE; in ibmasm_register_uart()
48 enable_uart_interrupts(sp->base_address); in ibmasm_register_uart()
56 disable_uart_interrupts(sp->base_address); in ibmasm_unregister_uart()
/drivers/input/serio/
A Dxilinx_ps2.c92 sr = in_be32(drvdata->base_address + XPS2_STATUS_OFFSET); in xps2_recv()
112 intr_sr = in_be32(drvdata->base_address + XPS2_IPISR_OFFSET); in xps2_interrupt()
163 sr = in_be32(drvdata->base_address + XPS2_STATUS_OFFSET); in sxps2_write()
167 out_be32(drvdata->base_address + XPS2_TX_DATA_OFFSET, c); in sxps2_write()
210 out_be32(drvdata->base_address + XPS2_GIER_OFFSET, 0x00); in sxps2_close()
211 out_be32(drvdata->base_address + XPS2_IPIER_OFFSET, 0x00); in sxps2_close()
272 drvdata->base_address = ioremap(phys_addr, remap_size); in xps2_of_probe()
273 if (drvdata->base_address == NULL) { in xps2_of_probe()
281 out_be32(drvdata->base_address + XPS2_IPIER_OFFSET, 0); in xps2_of_probe()
290 (unsigned long long)phys_addr, drvdata->base_address, in xps2_of_probe()
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/drivers/pinctrl/bcm/
A Dpinctrl-ns2-mux.c574 void __iomem *base_address; in ns2_pinmux_set() local
609 base_address = pinctrl->base0; in ns2_pinmux_set()
613 base_address = pinctrl->base1; in ns2_pinmux_set()
660 void __iomem *base_address; in ns2_pin_set_enable() local
662 base_address = pinctrl->pinconf_base; in ns2_pin_set_enable()
706 void __iomem *base_address; in ns2_pin_set_slew() local
708 base_address = pinctrl->pinconf_base; in ns2_pin_set_slew()
747 void __iomem *base_address; in ns2_pin_set_pull() local
749 base_address = pinctrl->pinconf_base; in ns2_pin_set_pull()
796 void __iomem *base_address; in ns2_pin_set_strength() local
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A Dpinctrl-nsp-mux.c391 void __iomem *base_address; in nsp_pinmux_set() local
425 base_address = pinctrl->base0; in nsp_pinmux_set()
429 base_address = pinctrl->base1; in nsp_pinmux_set()
433 base_address = pinctrl->base2; in nsp_pinmux_set()
441 val = readl(base_address); in nsp_pinmux_set()
444 writel(val, base_address); in nsp_pinmux_set()
A Dpinctrl-nsp-gpio.c96 void __iomem *base_address; in nsp_set_bit() local
99 base_address = chip->io_ctrl; in nsp_set_bit()
101 base_address = chip->base; in nsp_set_bit()
103 val = readl(base_address + reg); in nsp_set_bit()
109 writel(val, base_address + reg); in nsp_set_bit()
/drivers/iio/adc/
A Dad7606_par.c125 insw((unsigned long)st->base_address, _buf, 1); in ad7606_par16_read_block()
133 insw((unsigned long)st->base_address, _buf, num); in ad7606_par16_read_block()
159 insb((unsigned long)st->base_address, _buf, 2); in ad7606_par8_read_block()
167 insb((unsigned long)st->base_address, _buf, num * 2); in ad7606_par8_read_block()
A Dad7606.h148 void __iomem *base_address; member
224 int ad7606_probe(struct device *dev, int irq, void __iomem *base_address,
/drivers/media/platform/nxp/imx-jpeg/
A Dmxc-jpeg-hw.c12 #define print_wrapper_reg(dev, base_address, reg_offset)\ argument
13 internal_print_wrapper_reg(dev, (base_address), #reg_offset,\
15 #define internal_print_wrapper_reg(dev, base_address, reg_name, reg_offset) {\ argument
17 val = readl((base_address) + (reg_offset));\
/drivers/gpu/drm/amd/include/
A Ddiscovery.h107 uint32_t base_address[]; /* variable number of Addresses */ member
125 uint32_t base_address[]; /* Base Address list. Corresponds to the num_base_address field*/ member
143 …DECLARE_FLEX_ARRAY(uint32_t, base_address); /* 32-bit Base Address list. Corresponds to the num_ba…
435 uint64_t base_address; member
/drivers/acpi/arm64/
A Diort.c818 u64 addr = rmr_desc->base_address, size = rmr_desc->length; in iort_rmr_alloc()
836 size = PAGE_ALIGN(size + offset_in_page(rmr_desc->base_address)); in iort_rmr_alloc()
839 rmr_desc->base_address, in iort_rmr_alloc()
840 rmr_desc->base_address + rmr_desc->length - 1, in iort_rmr_alloc()
861 u64 end, start = desc[i].base_address, length = desc[i].length; in iort_rmr_desc_check_overlap()
873 u64 e_start = desc[j].base_address; in iort_rmr_desc_check_overlap()
1518 res[num_res].start = smmu->base_address; in arm_smmu_v3_init_resources()
1519 res[num_res].end = smmu->base_address + in arm_smmu_v3_init_resources()
1590 smmu->base_address, in arm_smmu_v3_set_proximity()
1627 res[num_res].start = smmu->base_address; in arm_smmu_init_resources()
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A Dgtdt.c243 !gtdt_frame->base_address || !gtdt_frame->timer_interrupt) in gtdt_parse_timer_block()
274 frame->cntbase = gtdt_frame->base_address; in gtdt_parse_timer_block()
/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/common/
A Dia_css_common_io_types.h14 unsigned int base_address; member
/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/
A Ddev.c17 phys_addr_t base_address; member
119 sf_dev->bar_base_addr = table->base_address + (sf_index * table->sf_bar_length); in mlx5_sf_dev_add()
335 table->base_address = pci_resource_start(dev->pdev, 2); in mlx5_sf_dev_table_create()
/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_gmc.c1333 if (ranges[i].base_address >= ranges[i].limit_address) { in amdgpu_gmc_get_nps_memranges()
1337 nps_type, i, ranges[i].base_address, in amdgpu_gmc_get_nps_memranges()
1345 if (max(ranges[j].base_address, in amdgpu_gmc_get_nps_memranges()
1346 ranges[i].base_address) <= in amdgpu_gmc_get_nps_memranges()
1352 ranges[j].base_address, in amdgpu_gmc_get_nps_memranges()
1354 ranges[i].base_address, in amdgpu_gmc_get_nps_memranges()
1362 (ranges[i].base_address - in amdgpu_gmc_get_nps_memranges()
1370 ranges[i].limit_address - ranges[i].base_address + 1; in amdgpu_gmc_get_nps_memranges()
/drivers/gpu/drm/amd/display/dmub/inc/
A Ddmub_cmd.h6333 void *base_address; /**< CPU base address for ring's data */ member
6343 void *base_address; /**< CPU address for the ring's data */ member
6434 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); in dmub_rb_push_front()
6464 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; in dmub_rb_out_push_front()
6491 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; in dmub_rb_front()
6531 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; in dmub_rb_peek_offset()
6552 …const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rpt… in dmub_rb_out_front()
6600 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); in dmub_rb_flush_pending()
6621 rb->base_address = init_params->base_address; in dmub_rb_init()
6638 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : in dmub_rb_get_return_data()
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/drivers/net/wireless/rsi/
A Drsi_91x_usb.c504 u32 base_address, in rsi_usb_load_data_master_write() argument
518 status = rsi_usb_write_register_multiple(adapter, base_address, in rsi_usb_load_data_master_write()
525 base_address += block_size; in rsi_usb_load_data_master_write()
533 (adapter, base_address, in rsi_usb_load_data_master_write()
A Drsi_91x_sdio.c557 u32 base_address, in rsi_sdio_load_data_master_write() argument
568 msb_address = base_address >> 16; in rsi_sdio_load_data_master_write()
586 lsb_address = (u16)base_address; in rsi_sdio_load_data_master_write()
596 base_address += block_size; in rsi_sdio_load_data_master_write()
598 if ((base_address >> 16) != msb_address) { in rsi_sdio_load_data_master_write()
617 lsb_address = (u16)base_address; in rsi_sdio_load_data_master_write()
/drivers/acpi/
A Dviot.c163 node->mmio.base_address); in viot_get_iommu()
221 ep->address = node->mmio.base_address; in viot_parse_node()
/drivers/nfc/s3fwrn5/
A Dfirmware.h59 __u32 base_address; member

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