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Searched refs:base_reg (Results 1 – 25 of 43) sorted by relevance

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/drivers/accel/habanalabs/goya/
A Dgoya_coresight.c232 u64 base_reg; in goya_config_stm() local
252 WREG32(base_reg + 0xD64, 7); in goya_config_stm()
305 u64 base_reg; in goya_config_etf() local
345 WREG32(base_reg + 0x20, 0); in goya_config_etf()
357 WREG32(base_reg + 0x20, 1); in goya_config_etf()
359 WREG32(base_reg + 0x34, 0); in goya_config_etf()
360 WREG32(base_reg + 0x28, 0); in goya_config_etf()
487 u64 base_reg; in goya_config_funnel() local
507 u64 base_reg; in goya_config_bmon() local
517 WREG32(base_reg + 0x104, 1); in goya_config_bmon()
[all …]
/drivers/accel/habanalabs/gaudi/
A Dgaudi_coresight.c394 u64 base_reg; in gaudi_config_stm() local
414 WREG32(base_reg + 0xD64, 7); in gaudi_config_stm()
472 u64 base_reg; in gaudi_config_etf() local
512 WREG32(base_reg + 0x20, 0); in gaudi_config_etf()
524 WREG32(base_reg + 0x20, 1); in gaudi_config_etf()
526 WREG32(base_reg + 0x34, 0); in gaudi_config_etf()
527 WREG32(base_reg + 0x28, 0); in gaudi_config_etf()
701 u64 base_reg; in gaudi_config_funnel() local
721 u64 base_reg; in gaudi_config_bmon() local
730 WREG32(base_reg + 0x104, 1); in gaudi_config_bmon()
[all …]
/drivers/base/regmap/
A Dregcache-rbtree.c27 unsigned int base_reg; member
44 *base = rbnode->base_reg; in regcache_rbtree_get_base_top_reg()
102 unsigned int base_reg; in regcache_rbtree_insert() local
112 base_reg = rbnode->base_reg; in regcache_rbtree_insert()
276 offset = (rbnode->base_reg - base_reg) / map->reg_stride; in regcache_rbtree_insert_to_block()
307 rbnode->base_reg = base_reg; in regcache_rbtree_insert_to_block()
428 if (reg < base_reg) in regcache_rbtree_write()
481 if (base_reg > max) in regcache_rbtree_sync()
486 if (min > base_reg) in regcache_rbtree_sync()
523 if (base_reg > max) in regcache_rbtree_drop()
[all …]
A Dregmap-debugfs.c140 c->base_reg = i; in regmap_debugfs_get_dump_start()
170 return c->base_reg + (reg_offset * map->reg_stride); in regmap_debugfs_get_dump_start()
205 if (reg < c->base_reg) { in regmap_next_readable_reg()
206 ret = c->base_reg; in regmap_next_readable_reg()
403 c->base_reg, c->max_reg); in regmap_reg_ranges_read_file()
/drivers/crypto/intel/keembay/
A Docs-aes.c220 aes_dev->base_reg + AES_ACTIVE_OFFSET); in aes_a_op_termination()
235 aes_dev->base_reg + AES_ACTIVE_OFFSET); in aes_a_set_last_gcx()
244 aes_active_reg = ioread32(aes_dev->base_reg + in aes_a_wait_last_gcx()
269 aes_dev->base_reg + AES_ACTIVE_OFFSET); in aes_a_set_last_gcx_and_adata()
336 aes_dev->base_reg + AES_A_DMA_MSI_IER_OFFSET); in aes_irq_disable()
508 aes_dev->base_reg + AES_KEY_0_OFFSET + in ocs_aes_set_key()
1043 iowrite8(in_tag[i], aes_dev->base_reg + in ocs_aes_ccm_write_encrypted_tag()
1115 iowrite8(b0[i], aes_dev->base_reg + in ocs_aes_ccm_write_b0()
1156 aes_dev->base_reg + in ocs_aes_ccm_write_adata_len()
1279 tag[i] = ioread32(aes_dev->base_reg + in ccm_compare_tag_to_yr()
[all …]
A Dkeembay-ocs-ecc.c87 void __iomem *base_reg; member
137 return readl_poll_timeout((dev->base_reg + HW_OFFS_OCS_ECC_STATUS), in ocs_ecc_wait_idle()
146 ecc_dev->base_reg + HW_OFFS_OCS_ECC_COMMAND); in ocs_ecc_cmd_start()
159 memcpy_toio(dev->base_reg + HW_OFFS_OCS_ECC_DATA_IN, data_in, in ocs_ecc_write_cmd_and_data()
185 memcpy_fromio(cx_out, dev->base_reg + HW_OFFS_OCS_ECC_CX_DATA_OUT, in ocs_ecc_read_cx_out()
199 memcpy_fromio(cy_out, dev->base_reg + HW_OFFS_OCS_ECC_CY_DATA_OUT, in ocs_ecc_read_cy_out()
867 status = ioread32(ecc_dev->base_reg + HW_OFFS_OCS_ECC_ISR); in ocs_ecc_irq_handler()
868 iowrite32(status, ecc_dev->base_reg + HW_OFFS_OCS_ECC_ISR); in ocs_ecc_irq_handler()
896 ecc_dev->base_reg = devm_platform_ioremap_resource(pdev, 0); in kmb_ocs_ecc_probe()
897 if (IS_ERR(ecc_dev->base_reg)) { in kmb_ocs_ecc_probe()
[all …]
/drivers/accel/habanalabs/gaudi2/
A Dgaudi2_coresight.c1967 base_reg); in gaudi2_unlock_coresight_unit()
1975 u64 base_reg; in gaudi2_config_stm() local
1990 if (!base_reg) in gaudi2_config_stm()
2062 u64 base_reg; in gaudi2_config_etf() local
2077 if (!base_reg) in gaudi2_config_etf()
2302 u64 base_reg; in gaudi2_config_funnel() local
2317 if (!base_reg) in gaudi2_config_funnel()
2342 u64 base_reg; in gaudi2_config_bmon() local
2355 if (!base_reg) in gaudi2_config_bmon()
2443 u64 base_reg; in gaudi2_config_spmu() local
[all …]
/drivers/gpu/drm/imx/dcss/
A Ddcss-dtg.c80 void __iomem *base_reg; member
101 dcss_writel(val, dtg->base_reg + ofs); in dcss_dtg_write()
112 status = dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS); in dcss_dtg_irq_handler()
134 dtg->base_reg + DCSS_DTG_INT_MASK); in dcss_dtg_irq_config()
161 dtg->base_reg = devm_ioremap(dtg->dev, dtg_base, SZ_4K); in dcss_dtg_init()
162 if (!dtg->base_reg) { in dcss_dtg_init()
312 dtg->base_reg + DCSS_DTG_TC_CONTROL_STATUS); in dcss_dtg_shutoff()
345 status = dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS); in dcss_dtg_vblank_irq_enable()
347 dtg->base_reg + DCSS_DTG_INT_CONTROL); in dcss_dtg_vblank_irq_enable()
363 dtg->base_reg + DCSS_DTG_INT_CONTROL); in dcss_dtg_ctxld_kick_irq_enable()
[all …]
A Ddcss-blkctl.c26 void __iomem *base_reg; member
32 dcss_writel(0, blkctl->base_reg + DCSS_BLKCTL_CONTROL0); in dcss_blkctl_cfg()
35 blkctl->base_reg + DCSS_BLKCTL_CONTROL0); in dcss_blkctl_cfg()
38 blkctl->base_reg + DCSS_BLKCTL_RESET_CTRL); in dcss_blkctl_cfg()
49 blkctl->base_reg = devm_ioremap(dcss->dev, blkctl_base, SZ_4K); in dcss_blkctl_init()
50 if (!blkctl->base_reg) { in dcss_blkctl_init()
A Ddcss-ss.c64 void __iomem *base_reg; member
76 dcss_writel(val, ss->base_reg + ofs); in dcss_ss_write()
94 ss->base_reg = devm_ioremap(ss->dev, ss_base, SZ_4K); in dcss_ss_init()
95 if (!ss->base_reg) { in dcss_ss_init()
109 dcss_writel(0, ss->base_reg + DCSS_SS_SYS_CTRL); in dcss_ss_exit()
172 dcss_writel(0, ss->base_reg + DCSS_SS_SYS_CTRL); in dcss_ss_shutoff()
A Ddcss-dpr.c93 void __iomem *base_reg; member
138 ch->base_reg = devm_ioremap(dpr->dev, ch->base_ofs, SZ_4K); in dcss_dpr_ch_init_all()
139 if (!ch->base_reg) { in dcss_dpr_ch_init_all()
148 dcss_writel(0xff, ch->base_reg + DCSS_DPR_IRQ_MASK); in dcss_dpr_ch_init_all()
181 dcss_writel(0, ch->base_reg + DCSS_DPR_SYSTEM_CTRL0); in dcss_dpr_exit()
A Ddcss-scaler.c69 void __iomem *base_reg; member
305 ch->base_reg = devm_ioremap(scl->dev, ch->base_ofs, SZ_4K); in dcss_scaler_ch_init_all()
306 if (!ch->base_reg) { in dcss_scaler_ch_init_all()
343 dcss_writel(0, ch->base_reg + DCSS_SCALER_CTRL); in dcss_scaler_exit()
/drivers/clk/
A Dclk-en7523.c48 u32 base_reg; member
101 .base_reg = REG_GSW_CLK_DIV_SEL,
115 .base_reg = REG_EMI_CLK_DIV_SEL,
129 .base_reg = REG_BUS_CLK_DIV_SEL,
158 .base_reg = REG_SPI_CLK_DIV_SEL,
170 .base_reg = REG_NPU_CLK_DIV_SEL,
184 .base_reg = REG_CRYPTO_CLKSRC,
197 .base_reg = REG_GSW_CLK_DIV_SEL,
211 .base_reg = REG_EMI_CLK_DIV_SEL,
280 .base_reg = REG_CRYPTO_CLKSRC2,
[all …]
/drivers/gpu/drm/sun4i/
A Dsun8i_csc.c116 u32 base_reg; in sun8i_csc_set_coefficients() local
123 base_reg = SUN8I_CSC_COEFF(base, 0); in sun8i_csc_set_coefficients()
124 regmap_bulk_write(map, base_reg, table, 12); in sun8i_csc_set_coefficients()
129 base_reg = SUN8I_CSC_COEFF(base, i + 1); in sun8i_csc_set_coefficients()
131 base_reg = SUN8I_CSC_COEFF(base, i - 1); in sun8i_csc_set_coefficients()
133 base_reg = SUN8I_CSC_COEFF(base, i); in sun8i_csc_set_coefficients()
134 regmap_write(map, base_reg, table[i]); in sun8i_csc_set_coefficients()
/drivers/watchdog/
A Drdc321x_wdt.c51 int base_reg; member
67 rdc321x_wdt_device.base_reg, &val); in rdc321x_wdt_trigger()
70 rdc321x_wdt_device.base_reg, val); in rdc321x_wdt_trigger()
99 rdc321x_wdt_device.base_reg, RDC_CLS_TMR); in rdc321x_wdt_start()
103 rdc321x_wdt_device.base_reg, in rdc321x_wdt_start()
159 rdc321x_wdt_device.base_reg, &value); in rdc321x_wdt_ioctl()
232 rdc321x_wdt_device.base_reg = r->start; in rdc321x_wdt_probe()
246 rdc321x_wdt_device.base_reg, RDC_WDT_RST); in rdc321x_wdt_probe()
/drivers/media/dvb-frontends/
A Ddibx000_common.c105 dibx000_read_word(mst, mst->base_reg + 2); in dibx000_master_i2c_write()
112 dibx000_write_word(mst, mst->base_reg, data); in dibx000_master_i2c_write()
129 dibx000_write_word(mst, mst->base_reg+1, da); in dibx000_master_i2c_write()
161 dibx000_write_word(mst, mst->base_reg+1, da); in dibx000_master_i2c_read()
169 da = dibx000_read_word(mst, mst->base_reg); in dibx000_master_i2c_read()
188 return dibx000_write_word(mst, mst->base_reg + 3, (u16)(60000 / speed)); in dibx000_i2c_set_speed()
204 return dibx000_write_word(mst, mst->base_reg + 4, intf); in dibx000_i2c_select_interface()
277 tx[0] = (((mst->base_reg + 1) >> 8) & 0xff); in dibx000_i2c_gate_ctrl()
278 tx[1] = ((mst->base_reg + 1) & 0xff); in dibx000_i2c_gate_ctrl()
458 mst->base_reg = 1024; in dibx000_init_i2c_master()
[all …]
/drivers/net/dsa/mv88e6xxx/
A Dglobal2_scratch.c52 int base_reg, unsigned int offset, in mv88e6xxx_g2_scratch_get_bit() argument
55 int reg = base_reg + (offset / 8); in mv88e6xxx_g2_scratch_get_bit()
79 int base_reg, unsigned int offset, in mv88e6xxx_g2_scratch_set_bit() argument
82 int reg = base_reg + (offset / 8); in mv88e6xxx_g2_scratch_set_bit()
/drivers/bus/
A Duniphier-system-bus.c118 void __iomem *base_reg = priv->membase + UNIPHIER_SBC_BASE; in uniphier_system_bus_check_boot_swap() local
121 is_swapped = !(readl(base_reg) & UNIPHIER_SBC_BASE_BE); in uniphier_system_bus_check_boot_swap()
136 void __iomem *base_reg = priv->membase + UNIPHIER_SBC_BASE; in uniphier_system_bus_set_reg() local
171 writel(val, base_reg + UNIPHIER_SBC_STRIDE * i); in uniphier_system_bus_set_reg()
/drivers/input/keyboard/
A Dtm2-touchkey.c38 u8 base_reg; member
58 .base_reg = 0x00,
65 .base_reg = 0x00,
79 .base_reg = 0x00,
107 touchkey->variant->base_reg, data); in tm2_touchkey_led_brightness_set()
/drivers/clk/tegra/
A Dclk-tegra124.c188 .base_reg = PLLX_BASE,
222 .base_reg = PLLC_BASE,
276 .base_reg = PLLC2_BASE,
298 .base_reg = PLLC3_BASE,
357 .base_reg = PLLC4_BASE,
420 .base_reg = PLLM_BASE,
477 .base_reg = PLLE_BASE,
553 .base_reg = PLLP_BASE,
582 .base_reg = PLLA_BASE,
627 .base_reg = PLLD_BASE,
[all …]
A Dclk-tegra210.c1660 .base_reg = PLLX_BASE,
1711 .base_reg = PLLC_BASE,
1750 .base_reg = PLLC2_BASE,
1780 .base_reg = PLLC3_BASE,
1845 .base_reg = PLLC4_BASE,
1899 .base_reg = PLLM_BASE,
1971 .base_reg = PLLE_BASE,
2047 .base_reg = PLLP_BASE,
2120 .base_reg = PLLA_BASE,
2167 .base_reg = PLLD_BASE,
[all …]
A Dclk-tegra114.c184 .base_reg = PLLC_BASE,
235 .base_reg = PLLC2_BASE,
257 .base_reg = PLLC3_BASE,
306 .base_reg = PLLM_BASE,
346 .base_reg = PLLP_BASE,
376 .base_reg = PLLA_BASE,
412 .base_reg = PLLD_BASE,
430 .base_reg = PLLD2_BASE,
472 .base_reg = PLLU_BASE,
501 .base_reg = PLLX_BASE,
[all …]
A Dclk-tegra30.c359 .base_reg = PLLC_BASE,
388 .base_reg = PLLM_BASE,
409 .base_reg = PLLP_BASE,
427 .base_reg = PLLA_BASE,
444 .base_reg = PLLD_BASE,
461 .base_reg = PLLD2_BASE,
478 .base_reg = PLLU_BASE,
496 .base_reg = PLLX_BASE,
515 .base_reg = PLLE_BASE,
A Dclk-tegra20.c284 .base_reg = PLLC_BASE,
300 .base_reg = PLLM_BASE,
316 .base_reg = PLLP_BASE,
334 .base_reg = PLLA_BASE,
350 .base_reg = PLLD_BASE,
372 .base_reg = PLLU_BASE,
389 .base_reg = PLLX_BASE,
407 .base_reg = PLLE_BASE,
/drivers/clk/visconti/
A Dpll.h52 unsigned long base_reg; member

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