| /drivers/clk/ux500/ |
| A D | u8500_of_clk.c | 131 u32 bases[CLKRST_MAX]; in u8500_clk_init() local
144 for (i = 0; i < ARRAY_SIZE(bases); i++) { in u8500_clk_init()
151 bases[i] = r.start; in u8500_clk_init()
489 bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE); in u8500_clk_init()
493 bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE); in u8500_clk_init()
497 bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE); in u8500_clk_init()
501 bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE); in u8500_clk_init()
505 bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE); in u8500_clk_init()
509 bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE); in u8500_clk_init()
551 bases[CLKRST2_INDEX], BIT(6), in u8500_clk_init()
[all …]
|
| /drivers/gpu/host1x/ |
| A D | syncpt.c | 26 struct host1x_syncpt_base *bases = host->bases; in host1x_syncpt_base_request() local
30 if (!bases[i].requested) in host1x_syncpt_base_request()
36 bases[i].requested = true; in host1x_syncpt_base_request()
37 return &bases[i]; in host1x_syncpt_base_request()
282 struct host1x_syncpt_base *bases; in host1x_syncpt_init() local
291 bases = devm_kcalloc(host->dev, host->info->nb_bases, sizeof(*bases), in host1x_syncpt_init()
293 if (!bases) in host1x_syncpt_init()
302 bases[i].id = i; in host1x_syncpt_init()
306 host->bases = bases; in host1x_syncpt_init()
|
| A D | dev.h | 138 struct host1x_syncpt_base *bases; member
|
| /drivers/iommu/ |
| A D | rockchip-iommu.c | 111 void __iomem **bases; member
431 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_enable_stall()
452 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_disable_stall()
473 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_enable_paging()
494 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_disable_paging()
537 void __iomem *base = iommu->bases[index]; in log_iova()
947 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, in rk_iommu_enable()
1215 iommu->bases = devm_kcalloc(dev, num_res, sizeof(*iommu->bases), in rk_iommu_probe()
1217 if (!iommu->bases) in rk_iommu_probe()
1225 if (IS_ERR(iommu->bases[i])) in rk_iommu_probe()
[all …]
|
| /drivers/gpu/drm/nouveau/dispnv50/ |
| A D | base.c | 33 } bases[] = { in nv50_base_new() local
46 cid = nvif_mclass(&disp->disp->object, bases); in nv50_base_new()
52 return bases[cid].new(drm, head, bases[cid].oclass, pwndw); in nv50_base_new()
|
| /drivers/iommu/arm/arm-smmu/ |
| A D | arm-smmu-nvidia.c | 36 void __iomem *bases[MAX_SMMU_INSTANCES]; member
52 return nvidia_smmu->bases[inst] + (page << smmu->pgshift); in nvidia_smmu_page()
322 nvidia_smmu->bases[0] = smmu->base; in nvidia_smmu_impl_init()
330 nvidia_smmu->bases[i] = devm_ioremap_resource(dev, res); in nvidia_smmu_impl_init()
331 if (IS_ERR(nvidia_smmu->bases[i])) in nvidia_smmu_impl_init()
332 return ERR_CAST(nvidia_smmu->bases[i]); in nvidia_smmu_impl_init()
|
| /drivers/gpu/drm/exynos/ |
| A D | exynos_drm_scaler.c | 155 static unsigned int bases[] = { in scaler_set_src_base() local
163 scaler_write(src_buf->dma_addr[i], bases[i]); in scaler_set_src_base()
218 static unsigned int bases[] = { in scaler_set_dst_base() local
226 scaler_write(dst_buf->dma_addr[i], bases[i]); in scaler_set_dst_base()
|
| /drivers/net/wireless/broadcom/b43/ |
| A D | pio.c | 82 static const u16 bases[] = { in index_to_pioqueue_base() local
105 B43_WARN_ON(index >= ARRAY_SIZE(bases)); in index_to_pioqueue_base()
106 return bases[index]; in index_to_pioqueue_base()
|
| /drivers/gpu/drm/msm/ |
| A D | NOTES | 58 register interface is same, just different bases.)
|
| /drivers/platform/mellanox/ |
| A D | Kconfig | 59 are defined per system type bases and include the registers related
|
| /drivers/gpu/drm/i915/gt/ |
| A D | intel_engine_cs.c | 344 const struct engine_mmio_base *bases) in __engine_mmio_base() argument
349 if (GRAPHICS_VER(i915) >= bases[i].graphics_ver) in __engine_mmio_base()
353 GEM_BUG_ON(!bases[i].base); in __engine_mmio_base()
355 return bases[i].base; in __engine_mmio_base()
|
| /drivers/media/usb/gspca/ |
| A D | Kconfig | 437 Say Y here if you want support for Xirlink C-It bases cameras.
|
| /drivers/firmware/cirrus/ |
| A D | cs_dsp.c | 2097 __be32 bases[] = { xm_base, xm_base, ym_base, ym_base }; in cs_dsp_halo_create_regions() local
2099 return cs_dsp_create_regions(dsp, id, ver, ARRAY_SIZE(types), types, bases); in cs_dsp_halo_create_regions()
|