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Searched refs:bit_depth (Results 1 – 25 of 52) sorted by relevance

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/drivers/media/platform/raspberrypi/pisp_be/
A Dpisp_be_formats.h20 unsigned int bit_depth; member
62 .bit_depth = 8,
72 .bit_depth = 8,
81 .bit_depth = 8,
90 .bit_depth = 8,
136 .bit_depth = 8,
145 .bit_depth = 8,
154 .bit_depth = 8,
486 .bit_depth = 8,
494 .bit_depth = 16,
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/drivers/media/test-drivers/vivid/
A Dvivid-vid-common.c38 .bit_depth = { 16 },
47 .bit_depth = { 16 },
55 .bit_depth = { 16 },
63 .bit_depth = { 16 },
143 .bit_depth = { 16 },
151 .bit_depth = { 16 },
158 .bit_depth = { 16 },
166 .bit_depth = { 32 },
174 .bit_depth = { 32 },
219 .bit_depth = { 8 },
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A Dvivid-vid-out.c272 (dev->sink_rect.width * dev->fmt_out->bit_depth[p]) / 8; in vivid_update_format_out()
400 bytesperline = (mp->width * fmt->bit_depth[p]) >> 3; in vivid_try_fmt_vid_out()
402 max_bpl = (MAX_ZOOM * MAX_WIDTH * fmt->bit_depth[p]) >> 3; in vivid_try_fmt_vid_out()
416 (fmt->bit_depth[p] / fmt->vdownsampling[p])) / in vivid_try_fmt_vid_out()
417 (fmt->bit_depth[0] / fmt->vdownsampling[0]); in vivid_try_fmt_vid_out()
551 (dev->bytesperline_out[0] * dev->fmt_out->bit_depth[p]) / in vivid_s_fmt_vid_out()
552 dev->fmt_out->bit_depth[0]; in vivid_s_fmt_vid_out()
/drivers/gpu/drm/amd/display/dc/opp/dcn20/
A Ddcn20_opp.c53 enum test_pattern_color_format bit_depth; in opp2_set_disp_pattern_generator() local
76 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6; in opp2_set_disp_pattern_generator()
79 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; in opp2_set_disp_pattern_generator()
88 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; in opp2_set_disp_pattern_generator()
128 DPG_BIT_DEPTH, bit_depth, in opp2_set_disp_pattern_generator()
142 switch (bit_depth) { in opp2_set_disp_pattern_generator()
187 DPG_BIT_DEPTH, bit_depth, in opp2_set_disp_pattern_generator()
195 mode = (bit_depth == in opp2_set_disp_pattern_generator()
200 switch (bit_depth) { in opp2_set_disp_pattern_generator()
221 switch (bit_depth) { in opp2_set_disp_pattern_generator()
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/drivers/media/platform/verisilicon/
A Dhantro_v4l2.c89 hantro_check_depth_match(const struct hantro_fmt *fmt, int bit_depth) in hantro_check_depth_match() argument
97 if (!bit_depth) in hantro_check_depth_match()
98 bit_depth = HANTRO_DEFAULT_BIT_DEPTH; in hantro_check_depth_match()
107 return fmt_depth <= bit_depth; in hantro_check_depth_match()
109 return fmt_depth == bit_depth; in hantro_check_depth_match()
150 int bit_depth, bool need_postproc) in hantro_get_default_fmt() argument
159 hantro_check_depth_match(&formats[i], bit_depth)) in hantro_get_default_fmt()
167 hantro_check_depth_match(&formats[i], bit_depth)) in hantro_get_default_fmt()
252 if (!hantro_check_depth_match(fmt, ctx->bit_depth) && !enum_all_formats) in vidioc_enum_fmt()
272 if (!hantro_check_depth_match(fmt, ctx->bit_depth) && !enum_all_formats) in vidioc_enum_fmt()
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A Dhantro_drv.c284 if (sequence->bit_depth != 8 && sequence->bit_depth != 10) in hantro_try_ctrl()
320 int bit_depth = ctrl->p_new.p_vp9_frame->bit_depth; in hantro_vp9_s_ctrl() local
322 if (ctx->bit_depth == bit_depth) in hantro_vp9_s_ctrl()
325 return hantro_reset_raw_fmt(ctx, bit_depth, HANTRO_AUTO_POSTPROC); in hantro_vp9_s_ctrl()
344 int bit_depth = sps->bit_depth_luma_minus8 + 8; in hantro_hevc_s_ctrl() local
346 if (ctx->bit_depth == bit_depth) in hantro_hevc_s_ctrl()
349 return hantro_reset_raw_fmt(ctx, bit_depth, HANTRO_AUTO_POSTPROC); in hantro_hevc_s_ctrl()
368 int bit_depth = ctrl->p_new.p_av1_sequence->bit_depth; in hantro_av1_s_ctrl() local
375 if (ctx->bit_depth == bit_depth && in hantro_av1_s_ctrl()
379 return hantro_reset_raw_fmt(ctx, bit_depth, need_postproc); in hantro_av1_s_ctrl()
A Dhantro_v4l2.h27 int hantro_reset_raw_fmt(struct hantro_ctx *ctx, int bit_depth, bool need_postproc);
32 int bit_depth, bool need_postproc);
A Dhantro.h263 int bit_depth; member
336 u32 bit_depth : 4; member
A Dhantro_hevc.c112 size = (VERT_FILTER_RAM_SIZE * height64 * (num_tile_cols - 1) * ctx->bit_depth) / 8; in tile_buffer_reallocate()
120 size = (VERT_SAO_RAM_SIZE * height64 * (num_tile_cols - 1) * ctx->bit_depth) / 8; in tile_buffer_reallocate()
A Dhantro_g2_vp9_dec.c114 buf->vp9.bit_depth = dec_params->bit_depth; in update_dec_buf_info()
502 hantro_reg_write(ctx->dev, &g2_bit_depth_y, dec_params->bit_depth); in config_bit_depth()
503 hantro_reg_write(ctx->dev, &g2_bit_depth_c, dec_params->bit_depth); in config_bit_depth()
506 hantro_reg_write(ctx->dev, &g2_bit_depth_y_minus8, dec_params->bit_depth - 8); in config_bit_depth()
507 hantro_reg_write(ctx->dev, &g2_bit_depth_c_minus8, dec_params->bit_depth - 8); in config_bit_depth()
/drivers/staging/media/sunxi/cedrus/
A Dcedrus.c48 unsigned int bit_depth, max_depth; in cedrus_try_ctrl() local
55 bit_depth = max(sps->bit_depth_luma_minus8, in cedrus_try_ctrl()
63 if (bit_depth > max_depth) in cedrus_try_ctrl()
74 if (ctx->bit_depth < bit_depth) in cedrus_try_ctrl()
77 ctx->bit_depth = bit_depth; in cedrus_try_ctrl()
371 ctx->bit_depth = 8; in cedrus_open()
/drivers/gpu/drm/amd/display/dc/dce120/
A Ddce120_timing_generator.c805 enum test_pattern_color_format bit_depth; in dce120_timing_generator_set_test_pattern() local
827 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6; in dce120_timing_generator_set_test_pattern()
830 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; in dce120_timing_generator_set_test_pattern()
833 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10; in dce120_timing_generator_set_test_pattern()
836 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12; in dce120_timing_generator_set_test_pattern()
839 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; in dce120_timing_generator_set_test_pattern()
861 CRTC_TEST_PATTERN_COLOR_FORMAT, bit_depth); in dce120_timing_generator_set_test_pattern()
873 switch (bit_depth) { in dce120_timing_generator_set_test_pattern()
969 mode = (bit_depth == in dce120_timing_generator_set_test_pattern()
974 switch (bit_depth) { in dce120_timing_generator_set_test_pattern()
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/drivers/gpu/drm/amd/display/dc/optc/dcn10/
A Ddcn10_optc.c979 enum test_pattern_color_format bit_depth; in optc1_set_test_pattern() local
1003 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6; in optc1_set_test_pattern()
1006 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; in optc1_set_test_pattern()
1015 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; in optc1_set_test_pattern()
1037 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); in optc1_set_test_pattern()
1049 switch (bit_depth) { in optc1_set_test_pattern()
1137 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); in optc1_set_test_pattern()
1143 mode = (bit_depth == in optc1_set_test_pattern()
1148 switch (bit_depth) { in optc1_set_test_pattern()
1169 switch (bit_depth) { in optc1_set_test_pattern()
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/drivers/gpu/drm/amd/display/dc/dce110/
A Ddce110_timing_generator.c715 enum test_pattern_color_format bit_depth; in dce110_timing_generator_set_test_pattern() local
737 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6; in dce110_timing_generator_set_test_pattern()
740 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; in dce110_timing_generator_set_test_pattern()
749 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; in dce110_timing_generator_set_test_pattern()
800 bit_depth, in dce110_timing_generator_set_test_pattern()
815 switch (bit_depth) { in dce110_timing_generator_set_test_pattern()
927 bit_depth, in dce110_timing_generator_set_test_pattern()
937 mode = (bit_depth == in dce110_timing_generator_set_test_pattern()
942 switch (bit_depth) { in dce110_timing_generator_set_test_pattern()
966 switch (bit_depth) { in dce110_timing_generator_set_test_pattern()
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/drivers/media/platform/mediatek/vcodec/decoder/
A Dmtk_vcodec_dec_stateless.c499 if (frame->bit_depth == 10) { in mtk_vdec_s_ctrl()
501 } else if (frame->bit_depth != 8) { in mtk_vdec_s_ctrl()
502 mtk_v4l2_vdec_err(ctx, "VP9: bit_depth:%d", frame->bit_depth); in mtk_vdec_s_ctrl()
509 if (seq->bit_depth == 10) { in mtk_vdec_s_ctrl()
511 } else if (seq->bit_depth != 8) { in mtk_vdec_s_ctrl()
512 mtk_v4l2_vdec_err(ctx, "AV1: bit_depth:%d", seq->bit_depth); in mtk_vdec_s_ctrl()
/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_color.c684 int bit_depth) in __drm_3dlut_to_dc_3dlut() argument
715 __to_dc_lut3d_color(&lut0[lut_i], lut[i], bit_depth); in __drm_3dlut_to_dc_3dlut()
716 __to_dc_lut3d_color(&lut1[lut_i], lut[i + 1], bit_depth); in __drm_3dlut_to_dc_3dlut()
717 __to_dc_lut3d_color(&lut2[lut_i], lut[i + 2], bit_depth); in __drm_3dlut_to_dc_3dlut()
718 __to_dc_lut3d_color(&lut3[lut_i], lut[i + 3], bit_depth); in __drm_3dlut_to_dc_3dlut()
721 __to_dc_lut3d_color(&lut0[lut_i], lut[i], bit_depth); in __drm_3dlut_to_dc_3dlut()
/drivers/media/platform/rockchip/rkvdec/
A Drkvdec-vp9.c405 aligned_pitch = round_up(buf->vp9.width * buf->vp9.bit_depth, 512) / 8; in get_mv_base_addr()
431 aligned_pitch = round_up(ref_buf->vp9.width * ref_buf->vp9.bit_depth, 512) / 8; in config_ref_registers()
495 buf->vp9.bit_depth = dec_params->bit_depth; in update_dec_buf_info()
519 unsigned int y_len, uv_len, yuv_len, bit_depth, aligned_height, aligned_pitch, stream_len; in config_registers() local
553 bit_depth = dec_params->bit_depth; in config_registers()
557 bit_depth, in config_registers()
A Drkvdec.h47 unsigned int bit_depth : 4; member
/drivers/media/platform/chips-media/wave5/
A Dwave5-vpu-enc.c804 inst->bit_depth = 8; in wave5_vpu_enc_s_ctrl()
809 inst->bit_depth = 8; in wave5_vpu_enc_s_ctrl()
813 inst->bit_depth = 10; in wave5_vpu_enc_s_ctrl()
936 inst->bit_depth = 8; in wave5_vpu_enc_s_ctrl()
940 inst->bit_depth = 8; in wave5_vpu_enc_s_ctrl()
944 inst->bit_depth = 8; in wave5_vpu_enc_s_ctrl()
948 inst->bit_depth = 8; in wave5_vpu_enc_s_ctrl()
952 inst->bit_depth = 10; in wave5_vpu_enc_s_ctrl()
956 inst->bit_depth = 10; in wave5_vpu_enc_s_ctrl()
960 inst->bit_depth = 10; in wave5_vpu_enc_s_ctrl()
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/drivers/media/platform/qcom/iris/
A Diris_hfi_gen1_response.c59 event.bit_depth = pixel_depth->bit_depth; in iris_hfi_gen1_read_changed_params()
168 if (event.bit_depth || !event.pic_struct) { in iris_hfi_gen1_read_changed_params()
170 event.bit_depth, event.pic_struct); in iris_hfi_gen1_read_changed_params()
A Diris_hfi_gen1_defines.h296 u32 bit_depth; member
380 u32 bit_depth; member
A Diris_hfi_gen2_response.c592 if (subsc_params.bit_depth != BIT_DEPTH_8 || in iris_hfi_gen2_read_input_subcr_params()
595 subsc_params.bit_depth, subsc_params.coded_frames); in iris_hfi_gen2_read_input_subcr_params()
673 inst_hfi_gen2->src_subcr_params.bit_depth = pkt->payload[0]; in iris_hfi_gen2_handle_session_property()
835 subsc_params->bit_depth = inst->fw_caps[BIT_DEPTH].value; in iris_hfi_gen2_init_src_change_param()
/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dmpc.h1086 void (*program_bit_depth)(struct mpc *mpc, uint16_t bit_depth, int mpcc_id);
1109 void (*program_bit_depth)(struct mpc *mpc, uint16_t bit_depth, int mpcc_id);
/drivers/media/platform/qcom/venus/
A Dvdec.c140 !(inst->bit_depth == VIDC_BITDEPTH_10)) in find_format()
168 !(inst->bit_depth == VIDC_BITDEPTH_10)) in find_format_by_index()
1514 if (inst->bit_depth != ev_data->bit_depth) { in vdec_event_change()
1515 inst->bit_depth = ev_data->bit_depth; in vdec_event_change()
1516 if (inst->bit_depth == VIDC_BITDEPTH_10) in vdec_event_change()
1697 inst->bit_depth = VIDC_BITDEPTH_8; in vdec_open()
/drivers/staging/media/ipu3/
A Dipu3-css.c66 .bit_depth = 10,
74 .bit_depth = 10,
82 .bit_depth = 10,
90 .bit_depth = 10,
734 frame_sp_info->raw_bit_depth = css_queue_in->css_fmt->bit_depth; in imgu_css_pipeline_init()
743 frame_sp_info->raw_bit_depth = css_queue_out->css_fmt->bit_depth; in imgu_css_pipeline_init()
752 frame_sp_info->raw_bit_depth = css_queue_out->css_fmt->bit_depth; in imgu_css_pipeline_init()
761 frame_sp_info->raw_bit_depth = css_queue_vf->css_fmt->bit_depth; in imgu_css_pipeline_init()
923 frame_sp->info.raw_bit_depth = css_queue_in->css_fmt->bit_depth; in imgu_css_pipeline_init()
934 frame_sp->info.raw_bit_depth = css_queue_out->css_fmt->bit_depth; in imgu_css_pipeline_init()
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