| /drivers/soc/tegra/fuse/ |
| A D | fuse-tegra30.c | 141 .bit_offset = 0,
147 .bit_offset = 0,
153 .bit_offset = 0,
159 .bit_offset = 0,
165 .bit_offset = 0,
171 .bit_offset = 0,
177 .bit_offset = 0,
183 .bit_offset = 0,
189 .bit_offset = 0,
195 .bit_offset = 0,
[all …]
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| /drivers/pinctrl/ |
| A D | pinctrl-bm1880.c | 1031 _regval |= (0 << bit_offset); in bm1880_pinconf_drv_set()
1035 _regval |= (1 << bit_offset); in bm1880_pinconf_drv_set()
1039 _regval |= (2 << bit_offset); in bm1880_pinconf_drv_set()
1222 regval |= BIT(bit_offset); in bm1880_pinconf_cfg_set()
1226 regval |= BIT(bit_offset); in bm1880_pinconf_cfg_set()
1230 regval |= BIT(bit_offset); in bm1880_pinconf_cfg_set()
1235 regval |= BIT(bit_offset); in bm1880_pinconf_cfg_set()
1237 regval &= ~BIT(bit_offset); in bm1880_pinconf_cfg_set()
1242 regval |= BIT(bit_offset); in bm1880_pinconf_cfg_set()
1244 regval &= ~BIT(bit_offset); in bm1880_pinconf_cfg_set()
[all …]
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| /drivers/gpio/ |
| A D | gpio-xgene.c | 41 u32 bit_offset; in xgene_gpio_get() local
44 bit_offset = GPIO_BIT_OFFSET(offset); in xgene_gpio_get()
52 u32 setval, bit_offset; in __xgene_gpio_set() local
59 setval |= BIT(bit_offset); in __xgene_gpio_set()
61 setval &= ~BIT(bit_offset); in __xgene_gpio_set()
83 bit_offset = GPIO_BIT_OFFSET(offset); in xgene_gpio_get_direction()
95 u32 dirval, bit_offset; in xgene_gpio_dir_in() local
98 bit_offset = GPIO_BIT_OFFSET(offset); in xgene_gpio_dir_in()
103 dirval |= BIT(bit_offset); in xgene_gpio_dir_in()
116 u32 dirval, bit_offset; in xgene_gpio_dir_out() local
[all …]
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| /drivers/acpi/acpica/ |
| A D | hwregs.c | 69 if (!reg->bit_offset && reg->bit_width && in acpi_hw_get_access_bit_width()
200 u8 bit_offset; in acpi_hw_read() local
221 bit_width = reg->bit_offset + reg->bit_width; in acpi_hw_read()
222 bit_offset = reg->bit_offset; in acpi_hw_read()
230 if (bit_offset >= access_width) { in acpi_hw_read()
232 bit_offset -= access_width; in acpi_hw_read()
295 u8 bit_offset; in acpi_hw_write() local
312 bit_width = reg->bit_offset + reg->bit_width; in acpi_hw_write()
313 bit_offset = reg->bit_offset; in acpi_hw_write()
328 if (bit_offset >= access_width) { in acpi_hw_write()
[all …]
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| A D | dsopcode.c | 83 u32 bit_offset; in acpi_ds_init_buffer_field() local
127 bit_offset = offset; in acpi_ds_init_buffer_field()
144 bit_offset = offset; in acpi_ds_init_buffer_field()
153 bit_offset = 8 * offset; in acpi_ds_init_buffer_field()
162 bit_offset = 8 * offset; in acpi_ds_init_buffer_field()
171 bit_offset = 8 * offset; in acpi_ds_init_buffer_field()
180 bit_offset = 8 * offset; in acpi_ds_init_buffer_field()
196 if ((bit_offset + bit_count) > (8 * (u32)buffer_desc->buffer.length)) { in acpi_ds_init_buffer_field()
202 bit_offset, bit_count, in acpi_ds_init_buffer_field()
214 bit_offset, bit_count); in acpi_ds_init_buffer_field()
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| /drivers/gpu/drm/omapdrm/ |
| A D | tcm-sita.c | 87 unsigned long bit_offset = (offset > 0) ? offset / slot_bytes : 0; in l2r_t2b() local
88 unsigned long curr_bit = bit_offset; in l2r_t2b()
101 if (bit_offset > 0 && (*pos % slots_per_band != bit_offset)) { in l2r_t2b()
102 curr_bit = ALIGN(*pos, slots_per_band) + bit_offset; in l2r_t2b()
108 curr_bit = ALIGN(*pos, slot_stride) + bit_offset; in l2r_t2b()
139 if (bit_offset > 0) in l2r_t2b()
140 curr_bit = ALIGN(*pos, slots_per_band) + bit_offset; in l2r_t2b()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| A D | bit.c | 30 if (likely(bios->bit_offset)) { in bit_entry()
31 u8 entries = nvbios_rd08(bios, bios->bit_offset + 10); in bit_entry()
32 u32 entry = bios->bit_offset + 12; in bit_entry()
42 entry += nvbios_rd08(bios, bios->bit_offset + 9); in bit_entry()
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| A D | base.c | 189 bios->bit_offset = nvbios_findstr(bios->data, bios->size, in nvkm_bios_new()
191 if (bios->bit_offset) in nvkm_bios_new()
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| /drivers/nvmem/ |
| A D | core.c | 32 int bit_offset; member
492 entry->bit_offset); in nvmem_populate_sysfs_cells()
590 cell->bit_offset = info->bit_offset; in nvmem_cell_info_to_nvmem_cell_entry_nodup()
1608 int bit_offset = cell->bit_offset; in nvmem_shift_read_buffer_in_place() local
1614 bit_offset %= BITS_PER_BYTE; in nvmem_shift_read_buffer_in_place()
1618 *p = *b++ >> bit_offset; in nvmem_shift_read_buffer_in_place()
1625 *p = *b++ >> bit_offset; in nvmem_shift_read_buffer_in_place()
1711 int i, rc, nbits, bit_offset = cell->bit_offset; in nvmem_cell_prepare_write_buffer() local
1722 if (bit_offset) { in nvmem_cell_prepare_write_buffer()
1724 *b <<= bit_offset; in nvmem_cell_prepare_write_buffer()
[all …]
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| /drivers/net/wireless/ralink/rt2x00/ |
| A D | rt2x00reg.h | 148 u8 bit_offset; member
153 u16 bit_offset; member
158 u32 bit_offset; member
240 ((__field).bit_offset)) & \
248 ((__field).bit_offset); \
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| A D | rt73usb.c | 308 field.bit_offset = (3 * key->hw_key_idx); in rt73usb_config_shared_key()
309 field.bit_mask = 0x7 << field.bit_offset; in rt73usb_config_shared_key()
315 field.bit_offset = (3 * (key->hw_key_idx - 8)); in rt73usb_config_shared_key()
316 field.bit_mask = 0x7 << field.bit_offset; in rt73usb_config_shared_key()
2253 field.bit_offset = (queue_idx & 1) * 16; in rt73usb_conf_tx()
2254 field.bit_mask = 0xffff << field.bit_offset; in rt73usb_conf_tx()
2261 field.bit_offset = queue_idx * 4; in rt73usb_conf_tx()
2262 field.bit_mask = 0xf << field.bit_offset; in rt73usb_conf_tx()
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| /drivers/acpi/apei/ |
| A D | apei-base.c | 64 *val >>= entry->register_region.bit_offset; in __apei_exec_read_register()
104 val <<= entry->register_region.bit_offset; in __apei_exec_write_register()
110 valr &= ~(entry->mask << entry->register_region.bit_offset); in __apei_exec_write_register()
571 u32 bit_width, bit_offset, access_size_code, space_id; in apei_check_gar() local
574 bit_offset = reg->bit_offset; in apei_check_gar()
581 *paddr, bit_width, bit_offset, access_size_code, in apei_check_gar()
589 *paddr, bit_width, bit_offset, access_size_code, in apei_check_gar()
596 if (bit_width == 32 && bit_offset == 0 && (*paddr & 0x03) == 0 && in apei_check_gar()
603 if ((bit_width + bit_offset) > *access_bit_width) { in apei_check_gar()
606 *paddr, bit_width, bit_offset, access_size_code, in apei_check_gar()
[all …]
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| /drivers/irqchip/ |
| A D | irq-meson-gpio.c | 235 unsigned int bit_offset; in meson8_gpio_irq_sel_pin() local
238 bit_offset = REG_PIN_SEL_SHIFT(channel); in meson8_gpio_irq_sel_pin()
241 ctl->params->pin_sel_mask << bit_offset, in meson8_gpio_irq_sel_pin()
242 hwirq << bit_offset); in meson8_gpio_irq_sel_pin()
250 unsigned int bit_offset; in meson_a1_gpio_irq_sel_pin() local
252 bit_offset = ((channel % 2) == 0) ? 0 : 16; in meson_a1_gpio_irq_sel_pin()
256 ctl->params->pin_sel_mask << bit_offset, in meson_a1_gpio_irq_sel_pin()
257 hwirq << bit_offset); in meson_a1_gpio_irq_sel_pin()
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| /drivers/acpi/ |
| A D | processor_throttling.c | 463 throttling->control_register.bit_offset) > 32) { in acpi_processor_get_throttling_control()
470 throttling->status_register.bit_offset) > 32) { in acpi_processor_get_throttling_control()
755 u32 bit_width, bit_offset; in acpi_read_throttling_status() local
765 bit_offset = throttling->status_register.bit_offset; in acpi_read_throttling_status()
769 (u32) (bit_width + bit_offset)); in acpi_read_throttling_status()
771 *value = (u64) ((ptc_value >> bit_offset) & ptc_mask); in acpi_read_throttling_status()
787 u32 bit_width, bit_offset; in acpi_write_throttling_state() local
797 bit_offset = throttling->control_register.bit_offset; in acpi_write_throttling_state()
803 (u32) (ptc_value << bit_offset), in acpi_write_throttling_state()
804 (u32) (bit_width + bit_offset)); in acpi_write_throttling_state()
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| A D | acpi_lpit.c | 44 u64 mask = GENMASK_ULL(residency_info_ffh.gaddr.bit_offset + in lpit_read_residency_counter_us()
46 residency_info_ffh.gaddr.bit_offset); in lpit_read_residency_counter_us()
49 *counter >>= residency_info_ffh.gaddr.bit_offset; in lpit_read_residency_counter_us()
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| /drivers/clk/imx/ |
| A D | clk-imx8qxp-lpcg.c | 181 unsigned int bit_offset[IMX_LPCG_MAX_CLKS]; in imx_lpcg_parse_clks_from_dt() local
219 ret = of_property_read_u32_array(np, "clock-indices", bit_offset, in imx_lpcg_parse_clks_from_dt()
246 idx = bit_offset[i] / 4; in imx_lpcg_parse_clks_from_dt()
256 bit_offset[i], false); in imx_lpcg_parse_clks_from_dt()
276 idx = bit_offset[i] / 4; in imx_lpcg_parse_clks_from_dt()
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| /drivers/watchdog/ |
| A D | wdat_wdt.c | 147 x >>= gas->bit_offset; in wdat_wdt_run_action()
157 x >>= gas->bit_offset; in wdat_wdt_run_action()
165 x <<= gas->bit_offset; in wdat_wdt_run_action()
170 y = y & ~(mask << gas->bit_offset); in wdat_wdt_run_action()
181 x <<= gas->bit_offset; in wdat_wdt_run_action()
186 y = y & ~(mask << gas->bit_offset); in wdat_wdt_run_action()
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| /drivers/pinctrl/sprd/ |
| A D | pinctrl-sprd.h | 31 .bit_offset = (((a) >> BIT_OFFSET) & 0xff), \
48 unsigned long bit_offset; member
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| A D | pinctrl-sprd.c | 112 unsigned long bit_offset; member
453 pin->bit_offset) & PINCTRL_BIT_MASK(pin->bit_width); in sprd_pinconf_get()
728 << pin->bit_offset); in sprd_pinconf_set()
730 << pin->bit_offset; in sprd_pinconf_set()
798 pin->bit_offset) & PINCTRL_BIT_MASK(pin->bit_width); in sprd_pinconf_get_config()
1014 pin->bit_offset = sprd_soc_pin_info[i].bit_offset; in sprd_pinctrl_add_pins()
1033 pin->bit_offset, pin->bit_width, pin->reg); in sprd_pinctrl_add_pins()
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| /drivers/gpu/drm/vkms/ |
| A D | vkms_formats.c | 321 int bit_offset = (8 - bits_per_pixel) - rem_x * bits_per_pixel; in Rx_read_line() local
339 u8 val = ((*src_pixels) >> bit_offset) & mask; in Rx_read_line()
343 bit_offset += step_bit_offset; in Rx_read_line()
344 if (bit_offset < 0 || 8 <= bit_offset) { in Rx_read_line()
345 bit_offset = restart_bit_offset; in Rx_read_line()
352 u8 val = (*src_pixels >> bit_offset) & mask; in Rx_read_line()
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| /drivers/gpu/nova-core/ |
| A D | vbios.rs | 416 let tokens_start = image.bit_offset + header.header_size as usize; in from_id()
695 bit_offset: usize, field
836 let bit_offset = Self::find_byte_pattern(data, &bit_pattern)?; in find_bit_header()
837 let bit_header = BitHeader::new(&data[bit_offset..])?; in find_bit_header()
839 Ok((bit_header, bit_offset)) in find_bit_header()
882 let (bit_header, bit_offset) = PciAtBiosImage::find_bit_header(data_slice)?; in try_from()
887 bit_offset, in try_from()
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| /drivers/cpufreq/ |
| A D | pcc-cpufreq.c | 57 u8 bit_offset; member
490 doorbell.bit_offset = reg_resource->bit_offset; in pcc_cpufreq_evaluate()
496 doorbell.space_id, doorbell.bit_width, doorbell.bit_offset, in pcc_cpufreq_evaluate()
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| /drivers/xen/ |
| A D | xen-acpi-processor.c | 79 dst_cx->reg.bit_offset = 0; in push_cxx_to_hypervisor()
85 dst_cx->reg.bit_offset = 2; in push_cxx_to_hypervisor()
199 dst_pct->bit_offset = pct->bit_offset; in xen_copy_pct_data()
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| /drivers/gpu/drm/nouveau/include/nvkm/subdev/ |
| A D | bios.h | 15 u32 bit_offset; member
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| /drivers/clk/ti/ |
| A D | clkctrl.c | 52 int bit_offset; member
238 iter->bit_offset == clkspec->args[1]) { in _ti_omap4_clkctrl_xlate()
319 clkctrl_clk->bit_offset = bit; in _ti_clkctrl_clk_register()
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