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Searched refs:blk (Results 1 – 25 of 76) sorted by relevance

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/drivers/net/ethernet/intel/ice/
A Dice_flex_pipe.c641 fv_ext = hw->blk[blk].es.t + (prof * hw->blk[blk].es.fvw); in ice_find_prot_off()
778 hw->blk[blk].xlt1.t[ptype] = ptg; in ice_ptg_add_mv_ptype()
1144 &hw->blk[blk].xlt2.vsis[vsi]; in ice_vsig_add_mv_vsi()
1146 hw->blk[blk].xlt2.t[vsi] = vsig; in ice_vsig_add_mv_vsi()
1173 for (i = hw->blk[blk].masks.first; i < hw->blk[blk].masks.first + in ice_prof_has_mask_idx()
1484 memset(hw->blk[blk].masks.masks, 0, sizeof(hw->blk[blk].masks.masks)); in ice_init_prof_masks()
1487 i < hw->blk[blk].masks.first + hw->blk[blk].masks.count; i++) in ice_init_prof_masks()
1524 i < hw->blk[blk].masks.first + hw->blk[blk].masks.count; i++) in ice_alloc_prof_mask()
1584 mask_idx < hw->blk[blk].masks.first + hw->blk[blk].masks.count)) in ice_free_prof_mask()
1650 i < hw->blk[blk].masks.first + hw->blk[blk].masks.count; i++) { in ice_shutdown_prof_masks()
[all …]
A Dice_flow.c927 u8 fv_words = hw->blk[params->blk].es.fvw; in ice_flow_xtract_fld()
1099 if (hw->blk[params->blk].es.reverse) in ice_flow_xtract_fld()
1142 fv_words = hw->blk[params->blk].es.fvw; in ice_flow_xtract_raws()
1171 if (params->es_cnt >= hw->blk[params->blk].es.count || in ice_flow_xtract_raws()
1176 if (hw->blk[params->blk].es.reverse) in ice_flow_xtract_raws()
1383 ids = &hw->blk[blk].prof_id; in ice_flow_add_prof_sync()
1405 params->blk = blk; in ice_flow_add_prof_sync()
1478 clear_bit(prof->id, hw->blk[blk].prof_id.id); in ice_flow_rem_prof_sync()
1577 u8 fv_words = hw->blk[blk].es.fvw; in ice_flow_set_parser_prof()
1591 if (hw->blk[blk].es.reverse) in ice_flow_set_parser_prof()
[all …]
A Dice_flex_pipe.h15 ice_find_prot_off(struct ice_hw *hw, enum ice_block blk, u8 prof, u16 fv_idx,
42 ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id,
47 ice_search_prof_id(struct ice_hw *hw, enum ice_block blk, u64 id);
49 ice_add_prof_id_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u64 hdl);
51 ice_rem_prof_id_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u64 hdl);
53 ice_flow_assoc_fdir_prof(struct ice_hw *hw, enum ice_block blk,
64 int ice_rem_prof(struct ice_hw *hw, enum ice_block blk, u64 id);
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_mem_input.h180 #define MI_DCP_MASK_SH_LIST(mask_sh, blk)\ argument
181 SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\
182 SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\
187 SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\
188 SFB(blk, GRPH_Y_END, GRPH_Y_END, mask_sh),\
189 SFB(blk, GRPH_PITCH, GRPH_PITCH, mask_sh),\
207 SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\
212 SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\
213 SFB(blk, GRPH_Y_END, GRPH_Y_END, mask_sh),\
214 SFB(blk, GRPH_PITCH, GRPH_PITCH, mask_sh),\
[all …]
/drivers/i2c/busses/
A Di2c-qup.c291 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_interrupt() local
485 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_tx_fifo_v1() local
948 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_read_rx_fifo_v1() local
985 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_v1() local
1027 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_xfer_v1() local
1071 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_one() local
1082 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_read_one() local
1154 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_count_v2() local
1185 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_mode_v2() local
1224 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_recv_data() local
[all …]
/drivers/net/phy/mscc/
A Dmscc_ptp.c71 switch (blk) { in vsc85xx_ts_read_csr()
118 blk == PROCESSOR; in vsc85xx_ts_write_csr()
121 switch (blk) { in vsc85xx_ts_write_csr()
322 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
324 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
326 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
328 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
330 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
556 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_eth_cmp1_init()
559 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_eth_cmp1_init()
[all …]
/drivers/gpu/drm/amd/display/dc/hwss/dce/
A Ddce_hwseq.h66 SRII(PIXEL_RATE_CNTL, blk, 0), \
67 SRII(PIXEL_RATE_CNTL, blk, 1), \
71 SRII(PIXEL_RATE_CNTL, blk, 5)
75 SRII(PIXEL_RATE_CNTL, blk, 1)
87 SRII(PIXEL_RATE_CNTL, blk, 1),\
88 SRII(PIXEL_RATE_CNTL, blk, 2),\
91 SRII(PIXEL_RATE_CNTL, blk, 5)
103 SRII(PIXEL_RATE_CNTL, blk, 1),\
104 SRII(PIXEL_RATE_CNTL, blk, 2),\
106 SRII(PIXEL_RATE_CNTL, blk, 4)
[all …]
/drivers/vdpa/vdpa_sim/
A Dvdpa_sim_blk.c69 if (blk->shared_backend) in vdpasim_blk_buffer_lock()
75 if (blk->shared_backend) in vdpasim_blk_buffer_unlock()
178 vdpasim_blk_buffer_lock(blk); in vdpasim_blk_handle_req()
201 vdpasim_blk_buffer_lock(blk); in vdpasim_blk_handle_req()
396 if (!blk->shared_backend) in vdpasim_blk_free()
397 kvfree(blk->buffer); in vdpasim_blk_free()
413 struct vdpasim_blk *blk; in vdpasim_blk_dev_add() local
434 blk = sim_to_blk(simdev); in vdpasim_blk_dev_add()
437 if (blk->shared_backend) { in vdpasim_blk_dev_add()
438 blk->buffer = shared_buffer; in vdpasim_blk_dev_add()
[all …]
/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_ctl.h119 enum dpu_wb blk);
128 enum dpu_cwb blk);
137 enum dpu_intf blk);
146 enum dpu_intf blk);
155 enum dpu_merge_3d blk);
164 enum dpu_sspp blk);
173 enum dpu_lm blk);
183 enum dpu_dspp blk, u32 dspp_sub_blk);
192 enum dpu_dsc blk);
/drivers/gpu/drm/arm/display/komeda/d71/
A Dd71_component.c421 get_valid_inputs(blk), in d71_layer_init()
539 1, get_valid_inputs(blk), 0, reg, in d71_wb_layer_init()
849 1, get_valid_inputs(blk), 1, reg, in d71_scaler_init()
958 1, get_valid_inputs(blk), 2, reg, in d71_splitter_init()
1139 get_valid_inputs(blk), in d71_improc_init()
1298 err = d71_layer_init(d71, blk, reg); in d71_probe_block()
1308 err = d71_compiz_init(d71, blk, reg); in d71_probe_block()
1312 err = d71_scaler_init(d71, blk, reg); in d71_probe_block()
1320 err = d71_merger_init(d71, blk, reg); in d71_probe_block()
1329 err = d71_improc_init(d71, blk, reg); in d71_probe_block()
[all …]
A Dd71_dev.c321 void d71_read_block_header(u32 __iomem *reg, struct block_header *blk) in d71_read_block_header() argument
325 blk->block_info = malidp_read32(reg, BLK_BLOCK_INFO); in d71_read_block_header()
326 if (BLOCK_INFO_BLK_TYPE(blk->block_info) == D71_BLK_TYPE_RESERVED) in d71_read_block_header()
329 blk->pipeline_info = malidp_read32(reg, BLK_PIPELINE_INFO); in d71_read_block_header()
333 blk->input_ids[i] = malidp_read32(reg + i, BLK_VALID_INPUT_ID0); in d71_read_block_header()
334 for (i = 0; i < PIPELINE_INFO_N_OUTPUTS(blk->pipeline_info); i++) in d71_read_block_header()
335 blk->output_ids[i] = malidp_read32(reg + i, BLK_OUTPUT_ID0); in d71_read_block_header()
353 struct block_header blk; in d71_enum_resources() local
447 d71_read_block_header(blk_base, &blk); in d71_enum_resources()
448 if (BLOCK_INFO_BLK_TYPE(blk.block_info) != D71_BLK_TYPE_RESERVED) { in d71_enum_resources()
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/drivers/usb/gadget/function/
A Df_midi2.c647 for (blk = 0; blk < ep->num_blks; blk++) { in process_ump_stream_msg()
1356 int i, blk, len; in assign_block_descriptors() local
1377 for (blk = 0; blk < ep->num_blks; blk++) { in assign_block_descriptors()
1579 for (blk = 0; blk < ep->num_blks; blk++) { in f_midi2_create_card()
1876 int blk; in fill_midi2_class_desc() local
1882 for (blk = 0; blk < ep->num_blks; blk++) in fill_midi2_class_desc()
1883 cdesc->baAssoGrpTrmBlkID[blk] = ep->blks[blk].gtb_id; in fill_midi2_class_desc()
1959 for (blk = 0; blk < ep->num_blks; blk++) in f_midi2_bind()
2842 for (blk = 0; blk < SNDRV_UMP_MAX_BLOCKS && in f_midi2_alloc()
2843 opts->eps[i]->blks[blk]; blk++) { in f_midi2_alloc()
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/drivers/media/test-drivers/vivid/
A Dvivid-radio-tx.c29 unsigned blk; in vivid_radio_tx_write() local
50 blk = ktime_divns(timestamp, VIVID_RDS_NSEC_PER_BLK); in vivid_radio_tx_write()
51 if (blk - VIVID_RDS_GEN_BLOCKS >= dev->radio_tx_rds_last_block) in vivid_radio_tx_write()
52 dev->radio_tx_rds_last_block = blk - VIVID_RDS_GEN_BLOCKS + 1; in vivid_radio_tx_write()
60 if (blk == dev->radio_tx_rds_last_block || in vivid_radio_tx_write()
72 for (i = 0; i < size && blk > dev->radio_tx_rds_last_block; in vivid_radio_tx_write()
A Dvivid-radio-rx.c32 unsigned blk; in vivid_radio_rx_read() local
56 blk = ktime_divns(timestamp, VIVID_RDS_NSEC_PER_BLK); in vivid_radio_rx_read()
57 use_alternates = (blk % VIVID_RDS_GEN_BLOCKS) & 1; in vivid_radio_rx_read()
65 if (blk >= dev->radio_rx_rds_last_block + VIVID_RDS_GEN_BLOCKS) in vivid_radio_rx_read()
66 dev->radio_rx_rds_last_block = blk - VIVID_RDS_GEN_BLOCKS + 1; in vivid_radio_rx_read()
74 if (blk == dev->radio_rx_rds_last_block || !dev->radio_rx_rds_enabled || in vivid_radio_rx_read()
90 for (i = 0; i < size && blk > dev->radio_rx_rds_last_block; in vivid_radio_rx_read()
/drivers/mtd/
A Dftl.c690 uint32_t blk; in find_free() local
725 for (blk = 0; blk < part->BlocksPerUnit; blk++) in find_free()
727 if (blk == part->BlocksPerUnit) { in find_free()
737 return blk; in find_free()
797 uint32_t bsize, blk, le_virt_addr; in set_bam_entry() local
809 blk = (log_addr % bsize) / SECTOR_SIZE; in set_bam_entry()
837 if (le32_to_cpu(part->bam_cache[blk]) != old_addr) { in set_bam_entry()
849 part->bam_cache[blk] = le_virt_addr; in set_bam_entry()
893 blk = find_free(part); in ftl_write()
894 if (blk == 0) { in ftl_write()
[all …]
/drivers/crypto/marvell/octeontx2/
A Dotx2_cpt_common.h19 #define OTX2_CPT_RVU_FUNC_ADDR_S(blk, slot, offs) \ argument
20 (((blk) << 20) | ((slot) << 12) | (offs))
131 static inline void otx2_cpt_write64(void __iomem *reg_base, u64 blk, u64 slot, in otx2_cpt_write64() argument
135 OTX2_CPT_RVU_FUNC_ADDR_S(blk, slot, offs)); in otx2_cpt_write64()
138 static inline u64 otx2_cpt_read64(void __iomem *reg_base, u64 blk, u64 slot, in otx2_cpt_read64() argument
142 OTX2_CPT_RVU_FUNC_ADDR_S(blk, slot, offs)); in otx2_cpt_read64()
/drivers/firmware/cirrus/
A Dcs_dsp.c1199 blk->name = raw->name; in cs_dsp_coeff_parse_alg()
1215 &blk->name); in cs_dsp_coeff_parse_alg()
1233 if ((int)blk->ncoeff < 0) in cs_dsp_coeff_parse_alg()
1237 cs_dsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name); in cs_dsp_coeff_parse_alg()
1275 blk->name = raw->name; in cs_dsp_coeff_parse_coeff()
1285 &blk->name); in cs_dsp_coeff_parse_coeff()
1314 cs_dsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name); in cs_dsp_coeff_parse_coeff()
2169 struct wmfw_coeff_item *blk; in cs_dsp_load_coeff() local
2221 if (le32_to_cpu(blk->len) > firmware->size - pos - sizeof(*blk)) { in cs_dsp_load_coeff()
2243 min(le32_to_cpu(blk->len), 100), blk->data); in cs_dsp_load_coeff()
[all …]
/drivers/soc/ixp4xx/
A Dixp4xx-npe.c515 } *blk; in npe_load_firmware() local
619 for (i = 0, blk = image->blocks; i < blocks; i++, blk++) { in npe_load_firmware()
621 || blk->offset < table_end) { in npe_load_firmware()
623 "firmware block #%i\n", blk->offset, i); in npe_load_firmware()
627 cb = (struct dl_codeblock*)&image->data[blk->offset]; in npe_load_firmware()
628 if (blk->type == FW_BLOCK_TYPE_INSTR) { in npe_load_firmware()
632 } else if (blk->type == FW_BLOCK_TYPE_DATA) { in npe_load_firmware()
638 "type 0x%X\n", i, blk->type); in npe_load_firmware()
641 if (blk->offset + sizeof(*cb) / 4 + cb->size > image->size) { in npe_load_firmware()
645 blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D', in npe_load_firmware()
[all …]
/drivers/platform/mellanox/
A Dmlxbf-pmc.c1112 if (strstr(blk, "tilenet")) { in mlxbf_pmc_event_list()
1115 } else if (strstr(blk, "tile")) { in mlxbf_pmc_event_list()
1121 } else if (strstr(blk, "trio")) { in mlxbf_pmc_event_list()
1136 } else if (strstr(blk, "mss")) { in mlxbf_pmc_event_list()
1152 } else if (strstr(blk, "ecc")) { in mlxbf_pmc_event_list()
1161 } else if (strstr(blk, "gic")) { in mlxbf_pmc_event_list()
1170 } else if (strstr(blk, "llt")) { in mlxbf_pmc_event_list()
1176 } else if (strstr(blk, "gga")) { in mlxbf_pmc_event_list()
1179 } else if (strstr(blk, "apt")) { in mlxbf_pmc_event_list()
1182 } else if (strstr(blk, "emi")) { in mlxbf_pmc_event_list()
[all …]
/drivers/pmdomain/imx/
A DMakefile5 obj-$(CONFIG_IMX8M_BLK_CTRL) += imx8m-blk-ctrl.o
6 obj-$(CONFIG_IMX8M_BLK_CTRL) += imx8mp-blk-ctrl.o
8 obj-$(CONFIG_IMX9_BLK_CTRL) += imx93-blk-ctrl.o
/drivers/nvmem/
A Dsprd-efuse.c194 static int sprd_efuse_raw_prog(struct sprd_efuse *efuse, u32 blk, bool doub, in sprd_efuse_raw_prog() argument
223 writel(*data, efuse->base + SPRD_EFUSE_MEM(blk)); in sprd_efuse_raw_prog()
237 "write error status %u of block %d\n", status, blk); in sprd_efuse_raw_prog()
244 writel(0, efuse->base + SPRD_EFUSE_MEM(blk)); in sprd_efuse_raw_prog()
254 static int sprd_efuse_raw_read(struct sprd_efuse *efuse, int blk, u32 *val, in sprd_efuse_raw_read() argument
269 *val = readl(efuse->base + SPRD_EFUSE_MEM(blk)); in sprd_efuse_raw_read()
284 "read error status %d of block %d\n", status, blk); in sprd_efuse_raw_read()
/drivers/staging/media/atomisp/pci/isp/kernels/bnlm/
A Dia_css_bnlm.host.c39 u32 blk, i; in bnlm_lut_encode() local
74 for (blk = 1; blk < total_blocks; blk++) { in bnlm_lut_encode()
75 u32 blk_offset = blk * block_size; in bnlm_lut_encode()
/drivers/gpu/drm/msm/disp/mdp5/
A Dmdp5_smp.c88 int blk = find_first_zero_bit(state->state, cnt); in smp_request_block() local
89 set_bit(blk, cs); in smp_request_block()
90 set_bit(blk, state->state); in smp_request_block()
223 u32 blk, val; in update_smp_state() local
225 for_each_set_bit(blk, *assigned, cnt) { in update_smp_state()
226 int idx = blk / 3; in update_smp_state()
227 int fld = blk % 3; in update_smp_state()
/drivers/gpu/drm/msm/adreno/
A Da6xx_gmu.c757 memcpy(bo->virt + blk->addr - bo->iova, blk->data, blk->size); in fw_block_mem()
766 const struct block_header *blk; in a6xx_gmu_fw_load() local
792 blk = (const struct block_header *) &blk->data[blk->size >> 2]) { in a6xx_gmu_fw_load()
793 if (blk->size == 0) in a6xx_gmu_fw_load()
797 reg_offset = (blk->addr - itcm_base) >> 2; in a6xx_gmu_fw_load()
800 blk->data, blk->size); in a6xx_gmu_fw_load()
802 reg_offset = (blk->addr - dtcm_base) >> 2; in a6xx_gmu_fw_load()
805 blk->data, blk->size); in a6xx_gmu_fw_load()
807 !fw_block_mem(&gmu->dcache, blk) && in a6xx_gmu_fw_load()
808 !fw_block_mem(&gmu->dummy, blk)) { in a6xx_gmu_fw_load()
[all …]
/drivers/net/wireless/quantenna/qtnfmac/pcie/
A Dpearl_pcie.c908 int blk, const u8 *pblk, const u8 *fw) in qtnf_ep_fw_send() argument
930 hdr->seqnum = cpu_to_le32(blk); in qtnf_ep_fw_send()
932 if (blk) in qtnf_ep_fw_send()
961 int blk = 0; in qtnf_ep_fw_load() local
966 while (blk < blk_count) { in qtnf_ep_fw_load()
976 if (!((blk + 1) & QTN_PCIE_FW_DLMASK) || in qtnf_ep_fw_load()
977 (blk == (blk_count - 1))) { in qtnf_ep_fw_load()
992 if (blk == (blk_count - 1)) { in qtnf_ep_fw_load()
995 blk -= last_round; in qtnf_ep_fw_load()
999 blk -= QTN_PCIE_FW_DLMASK; in qtnf_ep_fw_load()
[all …]

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