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Searched refs:block_sequence (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/amd/display/dc/core/
A Ddc_hw_sequencer.c726 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE], in hwss_build_fast_sequence()
769 block_sequence[*num_steps].func = OPTC_PIPE_CONTROL_LOCK; in hwss_build_fast_sequence()
777 block_sequence[*num_steps].func = DMUB_SEND_DMCUB_CMD; in hwss_build_fast_sequence()
811 block_sequence[*num_steps].func = HUBP_UPDATE_PLANE_ADDR; in hwss_build_fast_sequence()
830 block_sequence[*num_steps].func = DPP_SETUP_DPP; in hwss_build_fast_sequence()
866 block_sequence[*num_steps].func = MPC_SET_OUTPUT_CSC; in hwss_build_fast_sequence()
873 block_sequence[*num_steps].func = MPC_SET_OCSC_DEFAULT; in hwss_build_fast_sequence()
886 block_sequence[*num_steps].func = OPTC_PIPE_CONTROL_LOCK; in hwss_build_fast_sequence()
925 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE], in hwss_execute_sequence()
933 params = &(block_sequence[i].params); in hwss_execute_sequence()
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A Ddc_state.c336 memset(state->block_sequence, 0, sizeof(state->block_sequence)); in dc_state_destruct()
A Ddc.c4007 context->block_sequence, in commit_planes_for_stream_fast()
4013 context->block_sequence, in commit_planes_for_stream_fast()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
A Ddcn401_clk_mgr.c653 params = &clk_mgr401->block_sequence[i].params; in dcn401_execute_block_sequence()
655 switch (clk_mgr401->block_sequence[i].func) { in dcn401_execute_block_sequence()
773 struct dcn401_clk_mgr_block_sequence *block_sequence = clk_mgr401->block_sequence; in dcn401_build_update_bandwidth_clocks_sequence() local
882 block_sequence[num_steps].func = CLK_MGR401_INDICATE_DRR_STATUS; in dcn401_build_update_bandwidth_clocks_sequence()
1058 block_sequence[num_steps].func = CLK_MGR401_INDICATE_DRR_STATUS; in dcn401_build_update_bandwidth_clocks_sequence()
1087 struct dcn401_clk_mgr_block_sequence *block_sequence = clk_mgr401->block_sequence; in dcn401_build_update_display_clocks_sequence() local
1131 block_sequence[num_steps].func = CLK_MGR401_UPDATE_DTBCLK_DTO; in dcn401_build_update_display_clocks_sequence()
1163 block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO; in dcn401_build_update_display_clocks_sequence()
1167 block_sequence[num_steps].func = CLK_MGR401_UPDATE_DENTIST; in dcn401_build_update_display_clocks_sequence()
1195 block_sequence[num_steps].func = CLK_MGR401_UPDATE_DENTIST; in dcn401_build_update_display_clocks_sequence()
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A Ddcn401_clk_mgr.h104 struct dcn401_clk_mgr_block_sequence block_sequence[DCN401_CLK_MGR_MAX_SEQUENCE_SIZE]; member
/drivers/gpu/drm/amd/display/dc/hwss/
A Dhw_sequencer.h202 struct block_sequence { struct
544 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],
550 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],
/drivers/gpu/drm/amd/display/dc/inc/
A Dcore_types.h655 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE]; member

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