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Searched refs:boot_values (Results 1 – 18 of 18) sorted by relevance

/drivers/gpu/drm/amd/pm/swsmu/smu12/
A Dsmu_v12_0.c344 smu->smu_table.boot_values.socclk = 0; in smu_v12_0_get_vbios_bootup_values()
345 smu->smu_table.boot_values.dcefclk = 0; in smu_v12_0_get_vbios_bootup_values()
351 smu->smu_table.boot_values.pp_table_id = 0; in smu_v12_0_get_vbios_bootup_values()
361 smu->smu_table.boot_values.socclk = 0; in smu_v12_0_get_vbios_bootup_values()
362 smu->smu_table.boot_values.dcefclk = 0; in smu_v12_0_get_vbios_bootup_values()
378 &smu->smu_table.boot_values.socclk); in smu_v12_0_get_vbios_bootup_values()
383 &smu->smu_table.boot_values.dcefclk); in smu_v12_0_get_vbios_bootup_values()
388 &smu->smu_table.boot_values.vclk); in smu_v12_0_get_vbios_bootup_values()
393 &smu->smu_table.boot_values.dclk); in smu_v12_0_get_vbios_bootup_values()
400 &smu->smu_table.boot_values.fclk); in smu_v12_0_get_vbios_bootup_values()
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A Drenoir_ppt.c293 clock_limit = smu->smu_table.boot_values.uclk; in renoir_get_dpm_ultimate_freq()
297 clock_limit = smu->smu_table.boot_values.gfxclk; in renoir_get_dpm_ultimate_freq()
300 clock_limit = smu->smu_table.boot_values.socclk; in renoir_get_dpm_ultimate_freq()
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dppatomfwctrl.c453 boot_values->ulSocClk = 0; in pp_atomfwctrl_copy_vbios_bootup_values_3_2()
454 boot_values->ulDCEFClk = 0; in pp_atomfwctrl_copy_vbios_bootup_values_3_2()
457 boot_values->ulSocClk = frequency; in pp_atomfwctrl_copy_vbios_bootup_values_3_2()
460 boot_values->ulDCEFClk = frequency; in pp_atomfwctrl_copy_vbios_bootup_values_3_2()
463 boot_values->ulEClk = frequency; in pp_atomfwctrl_copy_vbios_bootup_values_3_2()
466 boot_values->ulVClk = frequency; in pp_atomfwctrl_copy_vbios_bootup_values_3_2()
469 boot_values->ulDClk = frequency; in pp_atomfwctrl_copy_vbios_bootup_values_3_2()
489 boot_values->ulSocClk = 0; in pp_atomfwctrl_copy_vbios_bootup_values_3_1()
490 boot_values->ulDCEFClk = 0; in pp_atomfwctrl_copy_vbios_bootup_values_3_1()
529 boot_values, fwinfo_3_2); in pp_atomfwctrl_get_vbios_bootup_values()
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A Dppatomfwctrl.h232 struct pp_atomfwctrl_bios_boot_up_values *boot_values);
/drivers/gpu/drm/amd/pm/swsmu/smu14/
A Dsmu_v14_0.c190 pptable_id = smu->smu_table.boot_values.pp_table_id; in smu_v14_0_init_pptable_microcode()
598 smu->smu_table.boot_values.socclk = 0; in smu_v14_0_get_vbios_bootup_values()
599 smu->smu_table.boot_values.dcefclk = 0; in smu_v14_0_get_vbios_bootup_values()
605 smu->smu_table.boot_values.pp_table_id = 0; in smu_v14_0_get_vbios_bootup_values()
612 smu->smu_table.boot_values.socclk = 0; in smu_v14_0_get_vbios_bootup_values()
613 smu->smu_table.boot_values.dcefclk = 0; in smu_v14_0_get_vbios_bootup_values()
627 smu->smu_table.boot_values.socclk = 0; in smu_v14_0_get_vbios_bootup_values()
628 smu->smu_table.boot_values.dcefclk = 0; in smu_v14_0_get_vbios_bootup_values()
1105 clock_limit = smu->smu_table.boot_values.uclk; in smu_v14_0_get_dpm_ultimate_freq()
1109 clock_limit = smu->smu_table.boot_values.gfxclk; in smu_v14_0_get_dpm_ultimate_freq()
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A Dsmu_v14_0_0_ppt.c786 clock_limit = smu->smu_table.boot_values.uclk; in smu_v14_0_1_get_dpm_ultimate_freq()
789 clock_limit = smu->smu_table.boot_values.fclk; in smu_v14_0_1_get_dpm_ultimate_freq()
793 clock_limit = smu->smu_table.boot_values.gfxclk; in smu_v14_0_1_get_dpm_ultimate_freq()
796 clock_limit = smu->smu_table.boot_values.socclk; in smu_v14_0_1_get_dpm_ultimate_freq()
800 clock_limit = smu->smu_table.boot_values.vclk; in smu_v14_0_1_get_dpm_ultimate_freq()
804 clock_limit = smu->smu_table.boot_values.dclk; in smu_v14_0_1_get_dpm_ultimate_freq()
908 clock_limit = smu->smu_table.boot_values.uclk; in smu_v14_0_0_get_dpm_ultimate_freq()
911 clock_limit = smu->smu_table.boot_values.fclk; in smu_v14_0_0_get_dpm_ultimate_freq()
915 clock_limit = smu->smu_table.boot_values.gfxclk; in smu_v14_0_0_get_dpm_ultimate_freq()
921 clock_limit = smu->smu_table.boot_values.vclk; in smu_v14_0_0_get_dpm_ultimate_freq()
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A Dsmu_v14_0_2_ppt.c517 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in smu_v14_0_2_set_default_dpm_table()
550 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; in smu_v14_0_2_set_default_dpm_table()
566 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in smu_v14_0_2_set_default_dpm_table()
582 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; in smu_v14_0_2_set_default_dpm_table()
598 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; in smu_v14_0_2_set_default_dpm_table()
614 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; in smu_v14_0_2_set_default_dpm_table()
630 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in smu_v14_0_2_set_default_dpm_table()
/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dsmu_v13_0.c612 smu->smu_table.boot_values.socclk = 0; in smu_v13_0_get_vbios_bootup_values()
613 smu->smu_table.boot_values.dcefclk = 0; in smu_v13_0_get_vbios_bootup_values()
619 smu->smu_table.boot_values.pp_table_id = 0; in smu_v13_0_get_vbios_bootup_values()
626 smu->smu_table.boot_values.socclk = 0; in smu_v13_0_get_vbios_bootup_values()
627 smu->smu_table.boot_values.dcefclk = 0; in smu_v13_0_get_vbios_bootup_values()
641 smu->smu_table.boot_values.socclk = 0; in smu_v13_0_get_vbios_bootup_values()
642 smu->smu_table.boot_values.dcefclk = 0; in smu_v13_0_get_vbios_bootup_values()
1799 *value = smu->smu_table.boot_values.uclk; in smu_v13_0_get_boot_freq_by_index()
1802 *value = smu->smu_table.boot_values.fclk; in smu_v13_0_get_boot_freq_by_index()
1812 *value = smu->smu_table.boot_values.vclk; in smu_v13_0_get_boot_freq_by_index()
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A Dsmu_v13_0_7_ppt.c594 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in smu_v13_0_7_set_default_dpm_table()
618 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; in smu_v13_0_7_set_default_dpm_table()
634 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in smu_v13_0_7_set_default_dpm_table()
650 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; in smu_v13_0_7_set_default_dpm_table()
666 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; in smu_v13_0_7_set_default_dpm_table()
682 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; in smu_v13_0_7_set_default_dpm_table()
698 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in smu_v13_0_7_set_default_dpm_table()
A Daldebaran_ppt.c417 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in aldebaran_set_default_dpm_table()
436 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; in aldebaran_set_default_dpm_table()
452 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in aldebaran_set_default_dpm_table()
468 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; in aldebaran_set_default_dpm_table()
531 smu->smu_table.boot_values.pp_table_id = 0; in aldebaran_setup_pptable()
A Dsmu_v13_0_0_ppt.c587 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in smu_v13_0_0_set_default_dpm_table()
620 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; in smu_v13_0_0_set_default_dpm_table()
636 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in smu_v13_0_0_set_default_dpm_table()
652 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; in smu_v13_0_0_set_default_dpm_table()
668 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; in smu_v13_0_0_set_default_dpm_table()
684 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; in smu_v13_0_0_set_default_dpm_table()
700 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in smu_v13_0_0_set_default_dpm_table()
/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dsmu_v11_0.c556 smu->smu_table.boot_values.socclk = 0; in smu_v11_0_get_vbios_bootup_values()
557 smu->smu_table.boot_values.dcefclk = 0; in smu_v11_0_get_vbios_bootup_values()
573 smu->smu_table.boot_values.socclk = 0; in smu_v11_0_get_vbios_bootup_values()
574 smu->smu_table.boot_values.dcefclk = 0; in smu_v11_0_get_vbios_bootup_values()
590 &smu->smu_table.boot_values.socclk); in smu_v11_0_get_vbios_bootup_values()
595 &smu->smu_table.boot_values.dcefclk); in smu_v11_0_get_vbios_bootup_values()
600 &smu->smu_table.boot_values.eclk); in smu_v11_0_get_vbios_bootup_values()
605 &smu->smu_table.boot_values.vclk); in smu_v11_0_get_vbios_bootup_values()
610 &smu->smu_table.boot_values.dclk); in smu_v11_0_get_vbios_bootup_values()
617 &smu->smu_table.boot_values.fclk); in smu_v11_0_get_vbios_bootup_values()
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A Dsienna_cichlid_ppt.c975 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in sienna_cichlid_set_default_dpm_table()
993 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; in sienna_cichlid_set_default_dpm_table()
1011 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in sienna_cichlid_set_default_dpm_table()
1029 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; in sienna_cichlid_set_default_dpm_table()
1051 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; in sienna_cichlid_set_default_dpm_table()
1073 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; in sienna_cichlid_set_default_dpm_table()
1092 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in sienna_cichlid_set_default_dpm_table()
1110 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in sienna_cichlid_set_default_dpm_table()
1128 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in sienna_cichlid_set_default_dpm_table()
1146 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in sienna_cichlid_set_default_dpm_table()
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A Darcturus_ppt.c380 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in arcturus_set_default_dpm_table()
398 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; in arcturus_set_default_dpm_table()
416 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in arcturus_set_default_dpm_table()
434 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; in arcturus_set_default_dpm_table()
937 smu->smu_table.boot_values.lclk / 100); in arcturus_emit_clk_levels()
A Dnavi10_ppt.c985 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in navi10_set_default_dpm_table()
1003 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; in navi10_set_default_dpm_table()
1021 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in navi10_set_default_dpm_table()
1039 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; in navi10_set_default_dpm_table()
1057 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; in navi10_set_default_dpm_table()
1075 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in navi10_set_default_dpm_table()
1093 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in navi10_set_default_dpm_table()
1111 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in navi10_set_default_dpm_table()
1129 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in navi10_set_default_dpm_table()
A Dvangogh_ppt.c901 clock_limit = smu->smu_table.boot_values.uclk; in vangogh_get_dpm_ultimate_freq()
904 clock_limit = smu->smu_table.boot_values.fclk; in vangogh_get_dpm_ultimate_freq()
908 clock_limit = smu->smu_table.boot_values.gfxclk; in vangogh_get_dpm_ultimate_freq()
911 clock_limit = smu->smu_table.boot_values.socclk; in vangogh_get_dpm_ultimate_freq()
914 clock_limit = smu->smu_table.boot_values.vclk; in vangogh_get_dpm_ultimate_freq()
917 clock_limit = smu->smu_table.boot_values.dclk; in vangogh_get_dpm_ultimate_freq()
/drivers/gpu/drm/amd/pm/swsmu/inc/
A Damdgpu_smu.h338 struct smu_bios_boot_up_values boot_values; member
/drivers/gpu/drm/amd/pm/swsmu/
A Damdgpu_smu.c1815 smu->smu_table.boot_values.dcefclk / 100); in smu_smc_hw_setup()

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