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Searched refs:bottom_pipe (Results 1 – 25 of 26) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/resource/dcn30/
A Ddcn30_resource.c1552 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe; in dcn30_split_stream_for_mpc_or_odm()
1570 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe; in dcn30_split_stream_for_mpc_or_odm()
1748 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe; in dcn30_internal_validate_bw() local
1750 top_pipe->bottom_pipe = bottom_pipe; in dcn30_internal_validate_bw()
1751 if (bottom_pipe) in dcn30_internal_validate_bw()
1789 if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe && in dcn30_internal_validate_bw()
1791 old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx; in dcn30_internal_validate_bw()
1832 else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe && in dcn30_internal_validate_bw()
1833 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe && in dcn30_internal_validate_bw()
1834 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state) in dcn30_internal_validate_bw()
[all …]
/drivers/gpu/drm/amd/display/dc/basics/
A Ddc_common.c57 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe)) in is_lower_pipe_tree_visible()
77 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe)) in is_pipe_tree_visible()
A Ddce_calcs.c2803 if (!pipe[i].stream || !pipe[i].bottom_pipe) in populate_initial_data()
2880 …data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.v… in populate_initial_data()
2881 …data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.vi… in populate_initial_data()
2883 pipe[i].bottom_pipe->plane_state->plane_size.surface_pitch); in populate_initial_data()
2884 …data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.… in populate_initial_data()
2885 …data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.… in populate_initial_data()
2887 pipe[i].bottom_pipe->plane_res.scl_data.ratios.horz.value); in populate_initial_data()
2889 pipe[i].bottom_pipe->plane_res.scl_data.ratios.vert.value); in populate_initial_data()
2890 switch (pipe[i].bottom_pipe->plane_state->rotation) { in populate_initial_data()
2915 if (!pipe[i].stream || pipe[i].bottom_pipe) in populate_initial_data()
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c1925 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe; in dcn32_split_stream_for_mpc_or_odm()
1984 pipe->prev_odm_pipe->bottom_pipe->bottom_pipe = pipe->bottom_pipe; in dcn32_apply_merge_split_flags_helper()
1988 pipe->prev_odm_pipe->bottom_pipe = pipe->bottom_pipe; in dcn32_apply_merge_split_flags_helper()
2013 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe; in dcn32_apply_merge_split_flags_helper() local
2015 top_pipe->bottom_pipe = bottom_pipe; in dcn32_apply_merge_split_flags_helper()
2055 if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe && in dcn32_apply_merge_split_flags_helper()
2057 old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx; in dcn32_apply_merge_split_flags_helper()
2098 else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe && in dcn32_apply_merge_split_flags_helper()
2099 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe && in dcn32_apply_merge_split_flags_helper()
2100 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state) in dcn32_apply_merge_split_flags_helper()
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_mall_phantom.c118 pipe->bottom_pipe = NULL; in merge_pipes_for_subvp()
130 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe; in merge_pipes_for_subvp() local
132 top_pipe->bottom_pipe = bottom_pipe; in merge_pipes_for_subvp()
133 if (bottom_pipe) in merge_pipes_for_subvp()
134 bottom_pipe->top_pipe = top_pipe; in merge_pipes_for_subvp()
137 pipe->bottom_pipe = NULL; in merge_pipes_for_subvp()
197 pipe = pipe->bottom_pipe; in get_num_free_pipes()
260 pipe = pipe->bottom_pipe; in assign_subvp_pipe()
324 pipe = pipe->bottom_pipe; in enough_pipes_for_subvp()
779 curr_pipe = curr_pipe->bottom_pipe; in enable_phantom_plane()
A Ddml2_dc_resource_mgmt.c164 mpc_pipe = mpc_pipe->bottom_pipe; in find_pipes_assigned_to_plane()
570 …top_pipe->bottom_pipe = &state->res_ctx.pipe_ctx[pipe_pool->pipes_assigned_to_plane[odm_slice][i]]; in add_plane_to_blend_tree()
575 state->res_ctx.pipe_ctx[pipe_pool->pipes_assigned_to_plane[odm_slice][i]].bottom_pipe = NULL; in add_plane_to_blend_tree()
727 pipe->top_pipe->bottom_pipe = pipe->bottom_pipe; in remove_pipes_from_blend_trees()
729 if (pipe->bottom_pipe) in remove_pipes_from_blend_trees()
730 pipe->bottom_pipe = pipe->top_pipe; in remove_pipes_from_blend_trees()
A Ddml2_translation_helper.c1219 pipe = pipe->bottom_pipe; in dml2_populate_pipe_to_plane_index_mapping()
/drivers/gpu/drm/amd/display/dc/core/
A Ddc_resource.c2000 pipe = pipe->bottom_pipe; in resource_get_dpp_pipes_for_opp_head()
2030 pipe = pipe->bottom_pipe; in resource_get_dpp_pipes_for_plane()
2234 if (pipe_a->bottom_pipe && pipe_b->bottom_pipe) { in resource_is_pipe_topology_changed()
2235 if (pipe_a->bottom_pipe->pipe_idx != pipe_b->bottom_pipe->pipe_idx) in resource_is_pipe_topology_changed()
2243 } else if (pipe_a->bottom_pipe || pipe_b->bottom_pipe) { in resource_is_pipe_topology_changed()
2528 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe; in acquire_first_split_pipe()
2529 if (split_pipe->bottom_pipe) in acquire_first_split_pipe()
3001 sec_pipe->bottom_pipe = NULL; in acquire_secondary_dpp_pipes_and_add_plane()
3053 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe; in resource_remove_dpp_pipes_for_plane_composition()
3266 new_dpp_pipe->bottom_pipe = last_dpp_pipe->bottom_pipe; in acquire_dpp_pipe_and_add_mpc_slice()
[all …]
A Ddc_hw_sequencer.c877 current_mpc_pipe = current_mpc_pipe->bottom_pipe; in hwss_build_fast_sequence()
910 if (!current_mpc_pipe->bottom_pipe && !current_mpc_pipe->next_odm_pipe && in hwss_build_fast_sequence()
918 current_mpc_pipe = current_mpc_pipe->bottom_pipe; in hwss_build_fast_sequence()
1125 while (bottom_pipe_ctx->bottom_pipe != NULL) in get_surface_tile_visual_confirm_color()
1126 bottom_pipe_ctx = bottom_pipe_ctx->bottom_pipe; in get_surface_tile_visual_confirm_color()
A Ddc_state.c157 if (cur_pipe->bottom_pipe) in dc_state_copy_internal()
158 cur_pipe->bottom_pipe = &dst_state->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx]; in dc_state_copy_internal()
/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calcs.c314 } else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state) { in pipe_ctx_to_e2e_pipe_params()
542 if (primary_pipe->bottom_pipe) { in split_stream_across_pipes()
543 ASSERT(primary_pipe->bottom_pipe != secondary_pipe); in split_stream_across_pipes()
544 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; in split_stream_across_pipes()
547 primary_pipe->bottom_pipe = secondary_pipe; in split_stream_across_pipes()
946 if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) { in dcn_validate_bandwidth()
1235 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; in dcn_validate_bandwidth()
1269 pipe->bottom_pipe = hsplit_pipe->bottom_pipe; in dcn_validate_bandwidth()
1270 if (hsplit_pipe->bottom_pipe) in dcn_validate_bandwidth()
1271 hsplit_pipe->bottom_pipe->top_pipe = pipe; in dcn_validate_bandwidth()
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn20/
A Ddcn20_resource.c1505 if (prev_odm_pipe->bottom_pipe && prev_odm_pipe->bottom_pipe->next_odm_pipe) { in dcn20_split_stream_for_odm()
1507 next_odm_pipe->bottom_pipe = prev_odm_pipe->bottom_pipe->next_odm_pipe; in dcn20_split_stream_for_odm()
1543 secondary_pipe->bottom_pipe = sec_bot_pipe; in dcn20_split_stream_for_mpc()
1553 if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) { in dcn20_split_stream_for_mpc()
1554 ASSERT(!secondary_pipe->bottom_pipe); in dcn20_split_stream_for_mpc()
1555 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; in dcn20_split_stream_for_mpc()
1777 odm_pipe->bottom_pipe = NULL; in dcn20_merge_pipes_for_validate()
1799 pipe->bottom_pipe = hsplit_pipe->bottom_pipe; in dcn20_merge_pipes_for_validate()
1800 if (hsplit_pipe->bottom_pipe) in dcn20_merge_pipes_for_validate()
1805 hsplit_pipe->bottom_pipe = NULL; in dcn20_merge_pipes_for_validate()
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource_helpers.c125 pipe->bottom_pipe = NULL; in dcn32_merge_pipes_for_subvp()
137 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe; in dcn32_merge_pipes_for_subvp() local
139 top_pipe->bottom_pipe = bottom_pipe; in dcn32_merge_pipes_for_subvp()
140 if (bottom_pipe) in dcn32_merge_pipes_for_subvp()
141 bottom_pipe->top_pipe = top_pipe; in dcn32_merge_pipes_for_subvp()
144 pipe->bottom_pipe = NULL; in dcn32_merge_pipes_for_subvp()
A Ddcn32_resource.c1678 curr_pipe = curr_pipe->bottom_pipe; in dcn32_enable_phantom_plane()
2693 if ((old_primary_pipe->next_odm_pipe) && (old_primary_pipe->next_odm_pipe->bottom_pipe) in find_idle_secondary_pipe_check_mpo()
2694 && (!primary_pipe->bottom_pipe)) in find_idle_secondary_pipe_check_mpo()
2695 next_odm_mpo_pipe = old_primary_pipe->next_odm_pipe->bottom_pipe; in find_idle_secondary_pipe_check_mpo()
2746 if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) { in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2747 idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx]; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2748 idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
A Ddcn20_hwseq.c735 pipe_ctx->bottom_pipe = NULL; in dcn20_plane_atomic_disable()
1401 temp_pipe = pipe->bottom_pipe; in dcn20_pipe_control_lock()
1405 temp_pipe = temp_pipe->bottom_pipe; in dcn20_pipe_control_lock()
1426 temp_pipe = temp_pipe->bottom_pipe; in dcn20_pipe_control_lock()
1433 if (lock && (pipe->bottom_pipe != NULL || !flip_immediate)) in dcn20_pipe_control_lock()
1441 temp_pipe = pipe->bottom_pipe; in dcn20_pipe_control_lock()
1445 temp_pipe = temp_pipe->bottom_pipe; in dcn20_pipe_control_lock()
1875 for (other_pipe = pipe->bottom_pipe; other_pipe != NULL; other_pipe = other_pipe->bottom_pipe) { in dcn20_calculate_vready_offset_for_group()
2176 pipe = pipe->bottom_pipe; in dcn20_program_front_end_for_ctx()
2324 pipe = pipe->bottom_pipe; in dcn20_post_unlock_program_front_end()
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/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
A Ddcn401_hwseq.c1088 if ((pipe_ctx->top_pipe != NULL) || (pipe_ctx->bottom_pipe != NULL)) { in dcn401_set_cursor_position()
1172 (pipe_ctx == pipe_ctx->top_pipe->bottom_pipe)) { in dcn401_set_cursor_position()
1348 pipe_ctx = pipe_ctx->bottom_pipe; in dcn401_wait_for_dcc_meta_propagation()
1741 for (mpc_pipe = odm_pipe; mpc_pipe != NULL; mpc_pipe = mpc_pipe->bottom_pipe) { in dcn401_perform_3dlut_wa_unlock()
1867 pipe_ctx->bottom_pipe = NULL; in dcn401_reset_back_end_for_pipe()
1913 for (other_pipe = pipe->bottom_pipe; other_pipe != NULL; other_pipe = other_pipe->bottom_pipe) { in dcn401_calculate_vready_offset_for_group()
2216 pipe = pipe->bottom_pipe; in dcn401_program_front_end_for_ctx()
2330 pipe = pipe->bottom_pipe; in dcn401_post_unlock_program_front_end()
/drivers/gpu/drm/amd/display/dc/hwss/dce60/
A Ddce60_hwseq.c312 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; in dce60_program_front_end_for_pipe()
/drivers/gpu/drm/amd/display/dc/hwss/dce110/
A Ddce110_hwseq.c1715 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; in dce110_apply_single_controller_ctx_to_hw()
2591 if (pipe_ctx->bottom_pipe) { in program_surface_visibility()
2594 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); in program_surface_visibility()
2596 if (pipe_ctx->bottom_pipe->plane_state->visible) { in program_surface_visibility()
2950 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; in dce110_program_front_end_for_pipe()
/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
A Ddcn10_hwseq.c1123 for (other_pipe = pipe->bottom_pipe; other_pipe != NULL; other_pipe = other_pipe->bottom_pipe) { in calculate_vready_offset_for_group()
1514 pipe_ctx->bottom_pipe = NULL; in dcn10_plane_atomic_disable()
2856 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe; in dcn10_update_mpcc()
2933 pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe; in update_scaler()
3632 if ((pipe_ctx->top_pipe != NULL) || (pipe_ctx->bottom_pipe != NULL)) { in dcn10_set_cursor_position()
3772 if (pipe_ctx->bottom_pipe) { in dcn10_set_cursor_position()
3774 pipe_ctx->bottom_pipe->plane_res.scl_data.viewport.y; in dcn10_set_cursor_position()
/drivers/gpu/drm/amd/display/dc/inc/
A Dcore_types.h469 struct pipe_ctx *bottom_pipe; member
/drivers/gpu/drm/amd/display/dc/
A Ddc_dmub_srv.c833 if (subvp_pipe->bottom_pipe) { in populate_subvp_cmd_pipe_info()
834 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx; in populate_subvp_cmd_pipe_info()
848 if (phantom_pipe->bottom_pipe) { in populate_subvp_cmd_pipe_info()
849 …pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.… in populate_subvp_cmd_pipe_info()
/drivers/gpu/drm/amd/display/dc/resource/dcn21/
A Ddcn21_resource.c823 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe; in dcn21_fast_validate_bw()
847 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; in dcn21_fast_validate_bw()
/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
A Ddcn201_hwseq.c426 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe; in dcn201_update_mpcc()
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddcn20_fpu.c1593 …pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pi… in dcn20_populate_dml_pipes_from_context()
1657 struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe; in dcn20_populate_dml_pipes_from_context()
1661 split_pipe = split_pipe->bottom_pipe; in dcn20_populate_dml_pipes_from_context()
/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
A Ddcn35_hwseq.c973 pipe_ctx->bottom_pipe = NULL; in dcn35_plane_atomic_disable()

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