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Searched refs:bus_width (Results 1 – 25 of 123) sorted by relevance

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/drivers/media/platform/rockchip/rkisp1/
A Drkisp1-common.c23 .bus_width = 10,
30 .bus_width = 10,
37 .bus_width = 10,
44 .bus_width = 10,
51 .bus_width = 12,
58 .bus_width = 12,
65 .bus_width = 12,
79 .bus_width = 8,
86 .bus_width = 8,
93 .bus_width = 8,
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/drivers/mtd/lpddr/
A Dlpddr2_nvm.c76 int bus_width; member
94 static inline u_int build_mr_cfgmask(u_int bus_width) in build_mr_cfgmask() argument
98 if (bus_width == 0x0004) /* x32 device */ in build_mr_cfgmask()
107 static inline u_int build_sr_ok_datamask(u_int bus_width) in build_sr_ok_datamask() argument
111 if (bus_width == 0x0004) /* x32 device */ in build_sr_ok_datamask()
125 val = map->pfow_base + offset*pcm_data->bus_width; in ow_reg_add()
338 if (pcm_data->bus_width == 0x0004) {/* 2x16 devices */ in lpddr2_nvm_write()
347 add += pcm_data->bus_width; in lpddr2_nvm_write()
348 tot_len += pcm_data->bus_width; in lpddr2_nvm_write()
422 pcm_data->bus_width = BUS_WIDTH; in lpddr2_nvm_probe()
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/drivers/memory/
A Dmvebu-devbus.c64 u32 bus_width; member
115 err = of_property_read_u32(node, "devbus,bus-width", &r->bus_width); in devbus_get_timing_params()
127 if (r->bus_width == 8) { in devbus_get_timing_params()
128 r->bus_width = 0; in devbus_get_timing_params()
129 } else if (r->bus_width == 16) { in devbus_get_timing_params()
130 r->bus_width = 1; in devbus_get_timing_params()
132 dev_err(devbus->dev, "invalid bus width %d\n", r->bus_width); in devbus_get_timing_params()
215 r->bus_width << ORION_DEV_WIDTH_SHIFT | in devbus_orion_set_timing_params()
236 value = r->bus_width << ARMADA_DEV_WIDTH_SHIFT | in devbus_armada_set_timing_params()
/drivers/mmc/core/
A Dmmc.c721 if (bus_width == MMC_BUS_WIDTH_1) in mmc_compare_ext_csds()
893 unsigned int bus_width) in __mmc_select_powerclass() argument
958 u32 bus_width, ext_csd_bits; in mmc_select_powerclass() local
965 bus_width = host->ios.bus_width; in mmc_select_powerclass()
967 if (bus_width == MMC_BUS_WIDTH_1) in mmc_select_powerclass()
1022 unsigned idx, bus_width = 0; in mmc_select_bus_width() local
1052 bus_width = bus_widths[idx]; in mmc_select_bus_width()
1066 err = bus_width; in mmc_select_bus_width()
1101 u32 bus_width, ext_csd_bits; in mmc_select_hs_ddr() local
1107 bus_width = host->ios.bus_width; in mmc_select_hs_ddr()
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A Dhost.c274 u32 bus_width, drv_type, cd_debounce_delay_ms; in mmc_of_parse() local
281 if (device_property_read_u32(dev, "bus-width", &bus_width) < 0) { in mmc_of_parse()
284 bus_width = 1; in mmc_of_parse()
287 switch (bus_width) { in mmc_of_parse()
298 "Invalid \"bus-width\" value %u!\n", bus_width); in mmc_of_parse()
A Dmmc_ops.c687 if (ios->bus_width == MMC_BUS_WIDTH_8) { in mmc_send_tuning()
690 } else if (ios->bus_width == MMC_BUS_WIDTH_4) { in mmc_send_tuning()
847 int mmc_bus_test(struct mmc_card *card, u8 bus_width) in mmc_bus_test() argument
851 if (bus_width == MMC_BUS_WIDTH_8) in mmc_bus_test()
853 else if (bus_width == MMC_BUS_WIDTH_4) in mmc_bus_test()
855 else if (bus_width == MMC_BUS_WIDTH_1) in mmc_bus_test()
/drivers/gpu/drm/atmel-hlcdc/
A Datmel_hlcdc_output.c44 u32 bus_width; in atmel_hlcdc_of_bus_fmt() local
47 ret = of_property_read_u32(ep, "bus-width", &bus_width); in atmel_hlcdc_of_bus_fmt()
53 switch (bus_width) { in atmel_hlcdc_of_bus_fmt()
/drivers/usb/isp1760/
A Disp1760-if.c207 u32 bus_width = 0; in isp1760_plat_probe() local
219 of_property_read_u32(dp, "bus-width", &bus_width); in isp1760_plat_probe()
220 if (bus_width == 16) in isp1760_plat_probe()
222 else if (bus_width == 8) in isp1760_plat_probe()
/drivers/dma/
A Dimg-mdc-dma.c141 unsigned int bus_width; member
228 if (IS_ALIGNED(dst, mdma->bus_width) && in mdc_list_desc_config()
229 IS_ALIGNED(src, mdma->bus_width)) in mdc_list_desc_config()
230 max_burst = mdma->bus_width * mdma->max_burst_mult; in mdc_list_desc_config()
237 mdc_set_read_width(ldesc, mdma->bus_width); in mdc_list_desc_config()
245 mdc_set_write_width(ldesc, mdma->bus_width); in mdc_list_desc_config()
251 mdc_set_read_width(ldesc, mdma->bus_width); in mdc_list_desc_config()
252 mdc_set_write_width(ldesc, mdma->bus_width); in mdc_list_desc_config()
359 if (width > mchan->mdma->bus_width) in mdc_check_slave_width()
924 mdma->bus_width = in mdc_dma_probe()
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A Dloongson1-apb-dma.c71 unsigned int bus_width; member
230 chan->bus_width = chan->dst_addr_width; in ls1x_dma_prep_lli()
235 chan->bus_width = chan->src_addr_width; in ls1x_dma_prep_lli()
265 lli->hw[LS1X_DMADESC_LENGTH] = buf_len / chan->bus_width; in ls1x_dma_prep_lli()
459 chan->bus_width; in ls1x_dma_tx_status()
A Dapple-admac.c747 u32 bus_width = readl_relaxed(ad->base + REG_BUS_WIDTH(adchan->no)) & in admac_device_config() local
753 bus_width |= BUS_WIDTH_8BIT; in admac_device_config()
757 bus_width |= BUS_WIDTH_16BIT; in admac_device_config()
761 bus_width |= BUS_WIDTH_32BIT; in admac_device_config()
778 bus_width |= BUS_WIDTH_FRAME_2_WORDS; in admac_device_config()
781 bus_width |= BUS_WIDTH_FRAME_4_WORDS; in admac_device_config()
787 writel_relaxed(bus_width, ad->base + REG_BUS_WIDTH(adchan->no)); in admac_device_config()
/drivers/mmc/host/
A Dcavium.c826 int clk_period = 0, power_class = 10, bus_width = 0; in cvm_mmc_set_ios() local
854 switch (ios->bus_width) { in cvm_mmc_set_ios()
856 bus_width = 2; in cvm_mmc_set_ios()
859 bus_width = 1; in cvm_mmc_set_ios()
862 bus_width = 0; in cvm_mmc_set_ios()
867 if (ios->bus_width && ios->timing == MMC_TIMING_MMC_DDR52) in cvm_mmc_set_ios()
868 bus_width |= 4; in cvm_mmc_set_ios()
881 FIELD_PREP(MIO_EMM_SWITCH_BUS_WIDTH, bus_width) | in cvm_mmc_set_ios()
951 u32 id, cmd_skew = 0, dat_skew = 0, bus_width = 0; in cvm_mmc_of_parse() local
986 if (bus_width == 8) in cvm_mmc_of_parse()
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A Dsdhci-pltfm.c76 u32 bus_width; in sdhci_get_property() local
82 (device_property_read_u32(dev, "bus-width", &bus_width) == 0 && in sdhci_get_property()
83 bus_width == 1)) in sdhci_get_property()
A Dmxs-mmc.c55 unsigned char bus_width; member
379 ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) | in mxs_mmc_adtc()
498 if (ios->bus_width == MMC_BUS_WIDTH_8) in mxs_mmc_set_ios()
499 host->bus_width = 2; in mxs_mmc_set_ios()
500 else if (ios->bus_width == MMC_BUS_WIDTH_4) in mxs_mmc_set_ios()
501 host->bus_width = 1; in mxs_mmc_set_ios()
503 host->bus_width = 0; in mxs_mmc_set_ios()
A Dtmio_mmc_core.c168 unsigned char bus_width) in tmio_mmc_set_bus_width() argument
174 if (bus_width == MMC_BUS_WIDTH_1) in tmio_mmc_set_bus_width()
176 else if (bus_width == MMC_BUS_WIDTH_8) in tmio_mmc_set_bus_width()
211 tmio_mmc_set_bus_width(host, host->mmc->ios.bus_width); in tmio_mmc_reset()
739 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4 || in tmio_mmc_start_data()
740 host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) { in tmio_mmc_start_data()
987 tmio_mmc_set_bus_width(host, ios->bus_width); in tmio_mmc_set_ios()
991 tmio_mmc_set_bus_width(host, ios->bus_width); in tmio_mmc_set_ios()
A Dsdhci-pxav2.c223 u32 bus_width; in pxav2_get_mmc_pdata() local
233 of_property_read_u32(np, "bus-width", &bus_width); in pxav2_get_mmc_pdata()
234 if (bus_width == 8) in pxav2_get_mmc_pdata()
A Dmeson-gx-mmc.c597 u32 bus_width, val; in meson_mmc_set_ios() local
623 switch (ios->bus_width) { in meson_mmc_set_ios()
625 bus_width = CFG_BUS_WIDTH_1; in meson_mmc_set_ios()
628 bus_width = CFG_BUS_WIDTH_4; in meson_mmc_set_ios()
631 bus_width = CFG_BUS_WIDTH_8; in meson_mmc_set_ios()
635 ios->bus_width); in meson_mmc_set_ios()
636 bus_width = CFG_BUS_WIDTH_4; in meson_mmc_set_ios()
641 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); in meson_mmc_set_ios()
/drivers/spi/
A Dspi-synquacer.c135 unsigned int bus_width; member
233 unsigned int speed, mode, bpw, cs, bus_width, transfer_mode; in synquacer_spi_config() local
245 bus_width = xfer->tx_nbits; in synquacer_spi_config()
248 bus_width = xfer->rx_nbits; in synquacer_spi_config()
259 bus_width == sspi->bus_width && bpw == sspi->bpw && in synquacer_spi_config()
341 val |= ((bus_width >> 1) << SYNQUACER_HSSPI_DMTRP_BUS_WIDTH_SHIFT); in synquacer_spi_config()
348 sspi->bus_width = bus_width; in synquacer_spi_config()
/drivers/media/platform/sunxi/sun6i-csi/
A Dsun6i_csi_bridge.c235 unsigned char bus_width = endpoint->bus.parallel.bus_width; in sun6i_csi_bridge_configure_parallel() local
253 if (bus_width == 16) in sun6i_csi_bridge_configure_parallel()
279 if (bus_width == 16) in sun6i_csi_bridge_configure_parallel()
299 switch (bus_width) { in sun6i_csi_bridge_configure_parallel()
312 dev_warn(dev, "unsupported bus width: %u\n", bus_width); in sun6i_csi_bridge_configure_parallel()
/drivers/staging/greybus/
A Dsdio.c594 u8 bus_width; in gb_mmc_set_ios() local
628 switch (ios->bus_width) { in gb_mmc_set_ios()
630 bus_width = GB_SDIO_BUS_WIDTH_1; in gb_mmc_set_ios()
634 bus_width = GB_SDIO_BUS_WIDTH_4; in gb_mmc_set_ios()
637 bus_width = GB_SDIO_BUS_WIDTH_8; in gb_mmc_set_ios()
640 request.bus_width = bus_width; in gb_mmc_set_ios()
/drivers/media/platform/st/stm32/stm32-dcmipp/
A Ddcmipp-core.c351 vep.bus.parallel.bus_width == 0) { in dcmipp_graph_notify_bound()
358 vep.bus.parallel.bus_width != 8) { in dcmipp_graph_notify_bound()
360 vep.bus.parallel.bus_width); in dcmipp_graph_notify_bound()
368 sink->bus.bus_width = vep.bus.parallel.bus_width; in dcmipp_graph_notify_bound()
/drivers/dma/xilinx/
A Dzynqmp_dma.c239 u32 bus_width; member
921 chan->bus_width = ZYNQMP_DMA_BUS_WIDTH_64; in zynqmp_dma_chan_probe()
924 err = of_property_read_u32(node, "xlnx,bus-width", &chan->bus_width); in zynqmp_dma_chan_probe()
930 if (chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_64 && in zynqmp_dma_chan_probe()
931 chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_128) { in zynqmp_dma_chan_probe()
1131 p->dst_addr_widths = BIT(zdev->chan->bus_width / 8); in zynqmp_dma_probe()
1132 p->src_addr_widths = BIT(zdev->chan->bus_width / 8); in zynqmp_dma_probe()
/drivers/media/platform/samsung/exynos4-is/
A Dfimc-reg.c588 u16 bus_width; member
603 u32 bus_width, cfg = 0; in fimc_hw_set_camera_source() local
617 bus_width = pix_desc[i].bus_width; in fimc_hw_set_camera_source()
630 if (bus_width == 8) in fimc_hw_set_camera_source()
632 else if (bus_width == 16) in fimc_hw_set_camera_source()
/drivers/gpu/drm/bridge/
A Dti-tfp410.c268 u32 bus_width = 24; in tfp410_parse_timings() local
293 of_property_read_u32(ep, "bus-width", &bus_width); in tfp410_parse_timings()
311 switch (bus_width) { in tfp410_parse_timings()
/drivers/edac/
A Dfsl_ddr_edac.c290 u32 bus_width; in fsl_mc_check() local
317 bus_width = (ddr_in32(pdata, FSL_MC_DDR_SDRAM_CFG) & in fsl_mc_check()
319 if (bus_width == 64) in fsl_mc_check()
342 if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) { in fsl_mc_check()

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