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Searched refs:bw_ctx (Results 1 – 25 of 71) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddcn30_fpu.c345 dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn30_fpu_calculate_wm_and_dlg()
351 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; in dcn30_fpu_calculate_wm_and_dlg()
370 …context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_fpu_calculate_wm_and_dlg()
374 …context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, … in dcn30_fpu_calculate_wm_and_dlg()
377 …context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, p… in dcn30_fpu_calculate_wm_and_dlg()
440 …context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_fpu_calculate_wm_and_dlg()
444 …context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, … in dcn30_fpu_calculate_wm_and_dlg()
447 …context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, p… in dcn30_fpu_calculate_wm_and_dlg()
453 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c; in dcn30_fpu_calculate_wm_and_dlg()
463 …context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_fpu_calculate_wm_and_dlg()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddcn31_fpu.c471 …if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[context->bw_ctx.dml.vba.VoltageLevel][context->… in dcn315_update_soc_for_wm_a()
472 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latenc… in dcn315_update_soc_for_wm_a()
477 context->bw_ctx.dml.soc.sr_exit_time_us = in dcn315_update_soc_for_wm_a()
489 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
523 …context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn31_calculate_wm_and_dlg_fp()
533 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a; in dcn31_calculate_wm_and_dlg_fp()
534 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a; in dcn31_calculate_wm_and_dlg_fp()
535 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; in dcn31_calculate_wm_and_dlg_fp()
565 context->bw_ctx.bw.dcn.clk.socclk_khz = 0; in dcn31_calculate_wm_and_dlg_fp()
570 context->bw_ctx.bw.dcn.clk.fclk_khz = 0; in dcn31_calculate_wm_and_dlg_fp()
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/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c1659 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; in dcn32_calculate_dlg_params()
1660 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; in dcn32_calculate_dlg_params()
1661 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; in dcn32_calculate_dlg_params()
1662 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; in dcn32_calculate_dlg_params()
1664 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; in dcn32_calculate_dlg_params()
1778 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; in dcn32_calculate_dlg_params()
1779 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; in dcn32_calculate_dlg_params()
1799 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg_v2(&context->bw_ctx.dml, in dcn32_calculate_dlg_params()
2561 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c; in dcn32_calculate_wm_and_dlg_fpu()
2593 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; in dcn32_calculate_wm_and_dlg_fpu()
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/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddcn20_fpu.c1154 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; in dcn20_calculate_dlg_params()
1155 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; in dcn20_calculate_dlg_params()
1156 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; in dcn20_calculate_dlg_params()
1157 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; in dcn20_calculate_dlg_params()
1162 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; in dcn20_calculate_dlg_params()
1163 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; in dcn20_calculate_dlg_params()
1165 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] in dcn20_calculate_dlg_params()
1217 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; in dcn20_calculate_dlg_params()
1218 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; in dcn20_calculate_dlg_params()
1235 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml, in dcn20_calculate_dlg_params()
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/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_utils.c184 context->bw_ctx.bw.dcn.clk.dispclk_khz = out_clks->dispclk_khz; in dml2_copy_clocks_to_dc_state()
185 context->bw_ctx.bw.dcn.clk.dcfclk_khz = out_clks->dcfclk_khz; in dml2_copy_clocks_to_dc_state()
187 context->bw_ctx.bw.dcn.clk.fclk_khz = out_clks->fclk_khz; in dml2_copy_clocks_to_dc_state()
188 context->bw_ctx.bw.dcn.clk.phyclk_khz = out_clks->phyclk_khz; in dml2_copy_clocks_to_dc_state()
189 context->bw_ctx.bw.dcn.clk.socclk_khz = out_clks->socclk_khz; in dml2_copy_clocks_to_dc_state()
286 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; in dml2_calculate_rq_and_dlg_params()
361 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; in dml2_calculate_rq_and_dlg_params()
362 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; in dml2_calculate_rq_and_dlg_params()
370 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; in dml2_calculate_rq_and_dlg_params()
371 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz ; in dml2_calculate_rq_and_dlg_params()
[all …]
A Ddml2_wrapper.c366 struct dml2_context *dml2 = context->bw_ctx.dml2; in call_dml_mode_support_and_programming()
401 struct dml2_context *dml2 = context->bw_ctx.dml2; in dml2_validate_and_build_resource()
419 context->bw_ctx.bw.dcn.clk.dtbclk_en = false; in dml2_validate_and_build_resource()
477 context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(in_dc, context); in dml2_validate_and_build_resource()
485 dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.a, &dml2->v20.dml_core_ctx); in dml2_validate_and_build_resource()
486 dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.b, &dml2->v20.dml_core_ctx); in dml2_validate_and_build_resource()
490 …memcpy(&context->bw_ctx.bw.dcn.watermarks.c, &dml2->v20.g6_temp_read_watermark_set, sizeof(context… in dml2_validate_and_build_resource()
491 dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.d, &dml2->v20.dml_core_ctx); in dml2_validate_and_build_resource()
494 context->bw_ctx.dml.vba.StutterPeriod = context->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterPeriod; in dml2_validate_and_build_resource()
498 if (context->bw_ctx.dml.vba.StutterPeriod < in_dc->debug.minimum_z8_residency_time && in dml2_validate_and_build_resource()
[all …]
/drivers/gpu/drm/amd/display/dc/core/
A Ddc_debug.c191 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
192 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
193 context->bw_ctx.bw.dcn.clk.dcfclk_khz, in context_clock_trace()
194 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in context_clock_trace()
195 context->bw_ctx.bw.dcn.clk.fclk_khz, in context_clock_trace()
196 context->bw_ctx.bw.dcn.clk.socclk_khz); in context_clock_trace()
199 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
200 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
201 context->bw_ctx.bw.dcn.clk.dcfclk_khz, in context_clock_trace()
203 context->bw_ctx.bw.dcn.clk.fclk_khz, in context_clock_trace()
[all …]
A Ddc_state.c237 dst_state->bw_ctx.dml2 = dst_dml2; in dc_state_copy()
238 if (src_state->bw_ctx.dml2) in dc_state_copy()
239 dml2_copy(dst_state->bw_ctx.dml2, src_state->bw_ctx.dml2); in dc_state_copy()
243 dml2_copy(dst_state->bw_ctx.dml2_dc_power_source, src_state->bw_ctx.dml2_dc_power_source); in dc_state_copy()
262 new_state->bw_ctx.dml2 = NULL; in dc_state_create_copy()
265 if (src_state->bw_ctx.dml2 && in dc_state_create_copy()
266 !dml2_create_copy(&new_state->bw_ctx.dml2, src_state->bw_ctx.dml2)) { in dc_state_create_copy()
272 …!dml2_create_copy(&new_state->bw_ctx.dml2_dc_power_source, src_state->bw_ctx.dml2_dc_power_source)… in dc_state_create_copy()
335 memset(&state->bw_ctx.bw, 0, sizeof(state->bw_ctx.bw)); in dc_state_destruct()
355 dml2_destroy(state->bw_ctx.dml2); in dc_state_free()
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_wrapper.c98 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; in dml21_calculate_rq_and_dlg_params()
106 context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0; in dml21_calculate_rq_and_dlg_params()
107 context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0; in dml21_calculate_rq_and_dlg_params()
108 context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0; in dml21_calculate_rq_and_dlg_params()
142 memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx], in dml21_calculate_rq_and_dlg_params()
151 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; in dml21_calculate_rq_and_dlg_params()
152 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; in dml21_calculate_rq_and_dlg_params()
154 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in dml21_calculate_rq_and_dlg_params()
161 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in dml21_calculate_rq_and_dlg_params()
169 …context->bw_ctx.bw.dcn.clk.num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, cont… in dml21_calculate_rq_and_dlg_params()
[all …]
A Ddml21_utils.c177 context->bw_ctx.bw.dcn.mall_ss_size_bytes += dc_pipe->surface_size_in_mall_bytes; in dml21_populate_mall_allocation_size()
181 context->bw_ctx.bw.dcn.mall_subvp_size_bytes += dc_pipe->surface_size_in_mall_bytes; in dml21_populate_mall_allocation_size()
231 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipe_ctx->plane_res.bw.dppclk_khz) in dml21_program_dc_pipe()
232 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipe_ctx->plane_res.bw.dppclk_khz; in dml21_program_dc_pipe()
385 …memset(&context->bw_ctx.bw.dcn.fams2_stream_base_params, 0, sizeof(union dmub_cmd_fams2_config) * … in dml21_build_fams2_programming()
386 …memset(&context->bw_ctx.bw.dcn.fams2_stream_sub_params, 0, sizeof(union dmub_cmd_fams2_config) * D… in dml21_build_fams2_programming()
388 …memset(&context->bw_ctx.bw.dcn.fams2_global_config, 0, sizeof(struct dmub_cmd_fams2_global_config)… in dml21_build_fams2_programming()
420 memcpy(&context->bw_ctx.bw.dcn.fams2_stream_sub_params_v2[num_fams2_streams], in dml21_build_fams2_programming()
503 memcpy(&context->bw_ctx.bw.dcn.fams2_global_config, in dml21_build_fams2_programming()
507 context->bw_ctx.bw.dcn.fams2_global_config.num_streams = num_fams2_streams; in dml21_build_fams2_programming()
[all …]
A Ddml21_translation_helper.c1154 …context->bw_ctx.bw.dcn.clk.dispclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4… in dml21_copy_clocks_to_dc_state()
1155 …context->bw_ctx.bw.dcn.clk.dcfclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x… in dml21_copy_clocks_to_dc_state()
1156 …context->bw_ctx.bw.dcn.clk.dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4… in dml21_copy_clocks_to_dc_state()
1157 …context->bw_ctx.bw.dcn.clk.fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.a… in dml21_copy_clocks_to_dc_state()
1158 …context->bw_ctx.bw.dcn.clk.idle_dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks… in dml21_copy_clocks_to_dc_state()
1159 …context->bw_ctx.bw.dcn.clk.idle_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dc… in dml21_copy_clocks_to_dc_state()
1161 …context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = in_ctx->v21.mode_programming.programming-… in dml21_copy_clocks_to_dc_state()
1162 …context->bw_ctx.bw.dcn.clk.p_state_change_support = in_ctx->v21.mode_programming.programming->uclk… in dml21_copy_clocks_to_dc_state()
1163 …context->bw_ctx.bw.dcn.clk.dtbclk_en = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.… in dml21_copy_clocks_to_dc_state()
1164 …context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.d… in dml21_copy_clocks_to_dc_state()
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/drivers/gpu/drm/amd/display/dc/resource/dce112/
A Ddce112_resource.c903 &context->bw_ctx.bw.dce)) in dce112_validate_bandwidth()
911 if (memcmp(&dc->current_state->bw_ctx.bw.dce, in dce112_validate_bandwidth()
912 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { in dce112_validate_bandwidth()
928 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, in dce112_validate_bandwidth()
929 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, in dce112_validate_bandwidth()
944 context->bw_ctx.bw.dce.stutter_mode_enable, in dce112_validate_bandwidth()
948 context->bw_ctx.bw.dce.all_displays_in_sync, in dce112_validate_bandwidth()
949 context->bw_ctx.bw.dce.dispclk_khz, in dce112_validate_bandwidth()
950 context->bw_ctx.bw.dce.sclk_khz, in dce112_validate_bandwidth()
951 context->bw_ctx.bw.dce.sclk_deep_sleep_khz, in dce112_validate_bandwidth()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calcs.c630 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
631 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
634 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
1153 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a; in dcn_validate_bandwidth()
1154 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a; in dcn_validate_bandwidth()
1155 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; in dcn_validate_bandwidth()
1169 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < in dcn_validate_bandwidth()
1171 context->bw_ctx.bw.dcn.clk.dispclk_khz = in dcn_validate_bandwidth()
1175 context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz / in dcn_validate_bandwidth()
1180 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in dcn_validate_bandwidth()
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/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
A Ddce110_clk_mgr.c183 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
185 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
187 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
189 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
191 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
205 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz in dce11_pplib_apply_display_requirements()
211 context->bw_ctx.bw.dce.sclk_khz); in dce11_pplib_apply_display_requirements()
224 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; in dce11_pplib_apply_display_requirements()
255 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce11_update_clocks()
270 context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk); in dce11_update_clocks()
/drivers/gpu/drm/amd/display/dc/resource/dce110/
A Ddce110_resource.c980 &context->bw_ctx.bw.dce)) in dce110_validate_bandwidth()
990 if (memcmp(&dc->current_state->bw_ctx.bw.dce, in dce110_validate_bandwidth()
991 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { in dce110_validate_bandwidth()
1007 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, in dce110_validate_bandwidth()
1008 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, in dce110_validate_bandwidth()
1023 context->bw_ctx.bw.dce.stutter_mode_enable, in dce110_validate_bandwidth()
1027 context->bw_ctx.bw.dce.all_displays_in_sync, in dce110_validate_bandwidth()
1028 context->bw_ctx.bw.dce.dispclk_khz, in dce110_validate_bandwidth()
1029 context->bw_ctx.bw.dce.sclk_khz, in dce110_validate_bandwidth()
1030 context->bw_ctx.bw.dce.sclk_deep_sleep_khz, in dce110_validate_bandwidth()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn301/
A Ddcn301_fpu.c434 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, in dcn301_fpu_calculate_wm_and_dlg()
435 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_fpu_calculate_wm_and_dlg()
439 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, in dcn301_fpu_calculate_wm_and_dlg()
440 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_fpu_calculate_wm_and_dlg()
444 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, in dcn301_fpu_calculate_wm_and_dlg()
445 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_fpu_calculate_wm_and_dlg()
450 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, in dcn301_fpu_calculate_wm_and_dlg()
451 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_fpu_calculate_wm_and_dlg()
457 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn301_fpu_calculate_wm_and_dlg()
461 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn301_fpu_calculate_wm_and_dlg()
[all …]
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_clk_mgr.c227 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
237 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
619 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
621 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
627 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
634 context->bw_ctx.bw.dce.sclk_khz); in dce11_pplib_apply_display_requirements()
647 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; in dce11_pplib_apply_display_requirements()
678 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce_update_clocks()
705 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce11_update_clocks()
732 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce112_update_clocks()
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/drivers/gpu/drm/amd/display/dc/dml/dcn35/
A Ddcn35_fpu.c530 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 384;/*per guide*/ in dcn35_populate_dml_pipes_from_context_fpu()
544 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn35_populate_dml_pipes_from_context_fpu()
550 context->bw_ctx.dml.ip.det_buffer_size_kbytes = in dcn35_populate_dml_pipes_from_context_fpu()
553 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn35_populate_dml_pipes_from_context_fpu()
568 context->bw_ctx.dml.vba.ODMCombinePolicy = in dcn35_populate_dml_pipes_from_context_fpu()
599 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency; in dcn35_decide_zstate_support()
602 bool allow_z10 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z10_residency; in dcn35_decide_zstate_support()
615 (int)context->bw_ctx.dml.vba.StutterPeriod); in dcn35_decide_zstate_support()
617 context->bw_ctx.bw.dcn.clk.zstate_support = support; in dcn35_decide_zstate_support()
/drivers/gpu/drm/amd/display/dc/dml/dcn314/
A Ddcn314_fpu.c392 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_14_DEFAULT_DET_SIZE; in dcn314_populate_dml_pipes_from_context_fpu()
402 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn314_populate_dml_pipes_from_context_fpu()
407 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64; in dcn314_populate_dml_pipes_from_context_fpu()
409 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn314_populate_dml_pipes_from_context_fpu()
413 context->bw_ctx.dml.ip.odm_combine_4to1_supported = true; in dcn314_populate_dml_pipes_from_context_fpu()
425 context->bw_ctx.dml.vba.ODMCombinePolicy = dm_odm_combine_policy_2to1; in dcn314_populate_dml_pipes_from_context_fpu()
/drivers/gpu/drm/amd/display/dc/resource/dcn30/
A Ddcn30_resource.c1380 struct display_mode_lib *dml = &context->bw_ctx.dml; in dcn30_set_mcif_arb_params()
1639 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn30_internal_validate_bw()
1645 context->bw_ctx.dml.vba.maxMpcComb = 0; in dcn30_internal_validate_bw()
1646 context->bw_ctx.dml.vba.VoltageLevel = 0; in dcn30_internal_validate_bw()
1668 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1686 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
1691 context->bw_ctx.dml.validate_max_state = false; in dcn30_internal_validate_bw()
1694 dml_log_mode_support_params(&context->bw_ctx.dml); in dcn30_internal_validate_bw()
1696 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1869 context->bw_ctx.dml.vba.VoltageLevel = vlevel; in dcn30_internal_validate_bw()
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/drivers/gpu/drm/amd/display/dc/dml/dcn351/
A Ddcn351_fpu.c563 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 384;/*per guide*/ in dcn351_populate_dml_pipes_from_context_fpu()
577 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn351_populate_dml_pipes_from_context_fpu()
583 context->bw_ctx.dml.ip.det_buffer_size_kbytes = in dcn351_populate_dml_pipes_from_context_fpu()
586 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn351_populate_dml_pipes_from_context_fpu()
601 context->bw_ctx.dml.vba.ODMCombinePolicy = in dcn351_populate_dml_pipes_from_context_fpu()
632 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency; in dcn351_decide_zstate_support()
638 context->bw_ctx.bw.dcn.clk.zstate_support = support; in dcn351_decide_zstate_support()
/drivers/gpu/drm/amd/display/dc/resource/dcn21/
A Ddcn21_resource.c800 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = in dcn21_fast_validate_bw()
802 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
804 if (vlevel > context->bw_ctx.dml.soc.num_states) { in dcn21_fast_validate_bw()
812 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = in dcn21_fast_validate_bw()
814 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
815 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn21_fast_validate_bw()
824 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn21_fast_validate_bw()
854 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
878 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn21_fast_validate_bw()
882 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
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/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
A Ddcn20_clk_mgr.c221 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn2_update_clocks()
349 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn2_update_clocks_fpga()
456 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; in dcn2_get_clock()
459 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz; in dcn2_get_clock()
462 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; in dcn2_get_clock()
465 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz; in dcn2_get_clock()
/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_hw_sequencer_debug.c478 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz, in dcn10_get_clock_states()
479 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in dcn10_get_clock_states()
480 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz, in dcn10_get_clock_states()
481 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz, in dcn10_get_clock_states()
482 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz, in dcn10_get_clock_states()
483 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz); in dcn10_get_clock_states()
/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource_helpers.c94 if (context->bw_ctx.bw.dcn.mall_subvp_size_bytes > 0) { in dcn32_helper_calculate_num_ways_for_subvp()
98 …return dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_s… in dcn32_helper_calculate_num_ways_for_subvp()
533 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down) in dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch()
711 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn32_subvp_vblank_admissable()
778 …if (dcn32_subvp_in_use(dc, context) && context->bw_ctx.bw.dcn.clk.dcfclk_khz <= MIN_SUBVP_DCFCLK_K… in dcn32_override_min_req_dcfclk()
779 context->bw_ctx.bw.dcn.clk.dcfclk_khz = MIN_SUBVP_DCFCLK_KHZ; in dcn32_override_min_req_dcfclk()

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