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Searched refs:bw_params (Results 1 – 25 of 59) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
A Ddcn315_clk_mgr.c391 if (!bw_params->wm_table.entries[i].valid) in dcn315_build_watermark_ranges()
487 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; in dcn315_clk_mgr_helper_populate_bw_params() local
489 …struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entri… in dcn315_clk_mgr_helper_populate_bw_params()
508 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz; in dcn315_clk_mgr_helper_populate_bw_params()
509 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz; in dcn315_clk_mgr_helper_populate_bw_params()
510 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz; in dcn315_clk_mgr_helper_populate_bw_params()
537 bw_params->clk_table.num_entries = i; in dcn315_clk_mgr_helper_populate_bw_params()
569 bw_params->vram_type = bios_info->memory_type; in dcn315_clk_mgr_helper_populate_bw_params()
574 bw_params->wm_table.entries[i].wm_inst = i; in dcn315_clk_mgr_helper_populate_bw_params()
576 if (i >= bw_params->clk_table.num_entries) { in dcn315_clk_mgr_helper_populate_bw_params()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn321/
A Ddcn321_fpu.c380 if (bw_params->clk_table.entries[i].memclk_mhz > 0) { in build_synthetic_soc_states()
382 if (bw_params->clk_table.entries[i].memclk_mhz <= bw_params->dc_mode_limit.memclk_mhz) in build_synthetic_soc_states()
385 if (bw_params->clk_table.entries[i].fclk_mhz > 0) { in build_synthetic_soc_states()
387 if (bw_params->clk_table.entries[i].fclk_mhz <= bw_params->dc_mode_limit.fclk_mhz) in build_synthetic_soc_states()
390 if (bw_params->clk_table.entries[i].dcfclk_mhz > 0) { in build_synthetic_soc_states()
392 if (bw_params->clk_table.entries[i].dcfclk_mhz <= bw_params->dc_mode_limit.dcfclk_mhz) in build_synthetic_soc_states()
408 min_fclk_mhz = bw_params->clk_table.entries[0].fclk_mhz; in build_synthetic_soc_states()
756 num_uclk_states = bw_params->clk_table.num_entries; in dcn321_update_bw_bounding_box_fpu()
772 bw_params->clk_table.entries[j].memclk_mhz * 16; in dcn321_update_bw_bounding_box_fpu()
830 if (!bw_params->clk_table.entries[i].dtbclk_mhz) { in dcn321_update_bw_bounding_box_fpu()
[all …]
A Ddcn321_fpu.h32 void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
A Ddcn314_clk_mgr.c494 if (!bw_params->wm_table.entries[i].valid) in dcn314_build_watermark_ranges()
621 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; in dcn314_clk_mgr_helper_populate_bw_params() local
622 …struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entri… in dcn314_clk_mgr_helper_populate_bw_params()
667 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz; in dcn314_clk_mgr_helper_populate_bw_params()
668 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz; in dcn314_clk_mgr_helper_populate_bw_params()
669 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz; in dcn314_clk_mgr_helper_populate_bw_params()
699 bw_params->clk_table.num_entries = i--; in dcn314_clk_mgr_helper_populate_bw_params()
736 bw_params->vram_type = bios_info->memory_type; in dcn314_clk_mgr_helper_populate_bw_params()
742 bw_params->wm_table.entries[i].wm_inst = i; in dcn314_clk_mgr_helper_populate_bw_params()
744 if (i >= bw_params->clk_table.num_entries) { in dcn314_clk_mgr_helper_populate_bw_params()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
A Ddcn401_clk_mgr.c222 if (!clk_mgr_base->bw_params) in dcn401_init_clocks()
326 clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz) || in dcn401_is_dc_mode_present()
836 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.… in dcn401_build_update_bandwidth_clocks_sequence()
1389 clk_mgr_base->bw_params->max_memclk_mhz = in dcn401_get_memclk_states_from_smu()
1397 …clk_mgr_base->bw_params->dc_mode_softmax_memclk = clk_mgr_base->bw_params->dc_mode_limit.memclk_mh… in dcn401_get_memclk_states_from_smu()
1421 if (clk_mgr_base->bw_params->num_channels == 0) { in dcn401_get_memclk_states_from_smu()
1429 clk_mgr->base.ctx->dc, clk_mgr_base->bw_params); in dcn401_get_memclk_states_from_smu()
1606 clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL); in dcn401_clk_mgr_construct()
1607 if (!clk_mgr->base.bw_params) { in dcn401_clk_mgr_construct()
1619 kfree(clk_mgr->base.bw_params); in dcn401_clk_mgr_construct()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddcn30_fpu.c294 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) { in dcn30_fpu_update_soc_for_wm_a()
361 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { in dcn30_fpu_calculate_wm_and_dlg()
408 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { in dcn30_fpu_calculate_wm_and_dlg()
569 struct clk_bw_params *bw_params, in dcn30_fpu_update_bw_bounding_box() argument
669 base->bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn3_fpu_build_wm_range_table()
691 base->bw_params->wm_table.nv_entries[WM_C].valid = true; in dcn3_fpu_build_wm_range_table()
700 base->bw_params->dummy_pstate_table[0].dram_speed_mts = 1600; in dcn3_fpu_build_wm_range_table()
702 base->bw_params->dummy_pstate_table[1].dram_speed_mts = 8000; in dcn3_fpu_build_wm_range_table()
704 base->bw_params->dummy_pstate_table[2].dram_speed_mts = 10000; in dcn3_fpu_build_wm_range_table()
706 base->bw_params->dummy_pstate_table[3].dram_speed_mts = 16000; in dcn3_fpu_build_wm_range_table()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
A Ddcn30_clk_mgr.c119 if (!clk_mgr_base->bw_params) in dcn3_init_clocks()
134 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn3_init_clocks()
140 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, in dcn3_init_clocks()
268 dc->clk_mgr->bw_params->dc_mode_softmax_memclk); in dcn3_update_clocks()
271 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].mem… in dcn3_update_clocks()
369 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].mem… in dcn3_set_hard_min_memclk()
385 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].mem… in dcn3_set_hard_max_memclk()
426 clk_mgr->base.ctx->dc, clk_mgr_base->bw_params); in dcn3_get_memclk_states_from_smu()
564 clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL); in dcn3_clk_mgr_construct()
565 if (!clk_mgr->base.bw_params) { in dcn3_clk_mgr_construct()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
A Ddcn35_clk_mgr.c755 if (!bw_params->wm_table.entries[i].valid) in dcn35_build_watermark_ranges()
905 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; in dcn35_clk_mgr_helper_populate_bw_params() local
906 …struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entri… in dcn35_clk_mgr_helper_populate_bw_params()
970 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz; in dcn35_clk_mgr_helper_populate_bw_params()
971 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz; in dcn35_clk_mgr_helper_populate_bw_params()
972 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz; in dcn35_clk_mgr_helper_populate_bw_params()
981 bw_params->clk_table.entries[i].wck_ratio = in dcn35_clk_mgr_helper_populate_bw_params()
1006 bw_params->clk_table.num_entries = i--; in dcn35_clk_mgr_helper_populate_bw_params()
1009 bw_params->clk_table.entries[i].socclk_mhz = in dcn35_clk_mgr_helper_populate_bw_params()
1013 bw_params->clk_table.entries[i].dppclk_mhz = in dcn35_clk_mgr_helper_populate_bw_params()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn302/
A Ddcn302_fpu.c220 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn302_fpu_update_bw_bounding_box()
224 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in dcn302_fpu_update_bw_bounding_box()
225 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box()
227 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn302_fpu_update_bw_bounding_box()
228 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) in dcn302_fpu_update_bw_bounding_box()
229 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn302_fpu_update_bw_bounding_box()
231 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn302_fpu_update_bw_bounding_box()
258 num_uclk_states = bw_params->clk_table.num_entries; in dcn302_fpu_update_bw_bounding_box()
273 bw_params->clk_table.entries[j].memclk_mhz * 16; in dcn302_fpu_update_bw_bounding_box()
329 if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0) in dcn302_fpu_update_bw_bounding_box()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn303/
A Ddcn303_fpu.c216 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn303_fpu_update_bw_bounding_box()
221 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn303_fpu_update_bw_bounding_box()
223 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn303_fpu_update_bw_bounding_box()
225 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn303_fpu_update_bw_bounding_box()
227 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn303_fpu_update_bw_bounding_box()
252 num_uclk_states = bw_params->clk_table.num_entries; in dcn303_fpu_update_bw_bounding_box()
267 bw_params->clk_table.entries[j].memclk_mhz * 16; in dcn303_fpu_update_bw_bounding_box()
278 bw_params->clk_table.entries[j].memclk_mhz * 16; in dcn303_fpu_update_bw_bounding_box()
295 bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn303_fpu_update_bw_bounding_box()
335 if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0) in dcn303_fpu_update_bw_bounding_box()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c205 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_pa… in dcn32_build_wm_range_table_fpu()
246 …clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table… in dcn32_build_wm_range_table_fpu()
248 …clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table… in dcn32_build_wm_range_table_fpu()
250 …clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table… in dcn32_build_wm_range_table_fpu()
252 …clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table… in dcn32_build_wm_range_table_fpu()
2840 if (bw_params->clk_table.entries[i].memclk_mhz <= bw_params->dc_mode_limit.memclk_mhz) in build_synthetic_soc_states()
2843 if (bw_params->clk_table.entries[i].fclk_mhz > 0) { in build_synthetic_soc_states()
2845 if (bw_params->clk_table.entries[i].fclk_mhz <= bw_params->dc_mode_limit.fclk_mhz) in build_synthetic_soc_states()
2850 if (bw_params->clk_table.entries[i].dcfclk_mhz <= bw_params->dc_mode_limit.dcfclk_mhz) in build_synthetic_soc_states()
3151 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn32_update_bw_bounding_box_fpu()
[all …]
A Ddcn32_fpu.h59 void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
67 void dcn32_patch_dpm_table(struct clk_bw_params *bw_params);
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
A Ddcn32_clk_mgr.c169 if (!clk_mgr_base->bw_params) in dcn32_init_clocks()
207 clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = in dcn32_init_clocks()
722 dc->clk_mgr->bw_params->dc_mode_softmax_memclk); in dcn32_update_clocks()
1007 clk_mgr_base->bw_params->max_memclk_mhz); in dcn32_set_hard_min_memclk()
1040 …clk_mgr_base->bw_params->dc_mode_softmax_memclk = clk_mgr_base->bw_params->dc_mode_limit.memclk_mh… in dcn32_get_memclk_states_from_smu()
1055 clk_mgr_base->bw_params->max_memclk_mhz = in dcn32_get_memclk_states_from_smu()
1063 dcn32_patch_dpm_table(clk_mgr_base->bw_params); in dcn32_get_memclk_states_from_smu()
1068 clk_mgr->base.ctx->dc, clk_mgr_base->bw_params); in dcn32_get_memclk_states_from_smu()
1212 clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL); in dcn32_clk_mgr_construct()
1213 if (!clk_mgr->base.bw_params) { in dcn32_clk_mgr_construct()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
A Ddcn316_clk_mgr.c356 if (!bw_params->wm_table.entries[i].valid) in dcn316_build_watermark_ranges()
374 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn316_build_watermark_ranges()
488 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; in dcn316_clk_mgr_helper_populate_bw_params() local
511 bw_params->clk_table.num_entries = j + 1; in dcn316_clk_mgr_helper_populate_bw_params()
530 bw_params->clk_table.entries[i].wck_ratio = 2; in dcn316_clk_mgr_helper_populate_bw_params()
533 bw_params->clk_table.entries[i].wck_ratio = 4; in dcn316_clk_mgr_helper_populate_bw_params()
548 bw_params->vram_type = bios_info->memory_type; in dcn316_clk_mgr_helper_populate_bw_params()
553 bw_params->wm_table.entries[i].wm_inst = i; in dcn316_clk_mgr_helper_populate_bw_params()
555 if (i >= bw_params->clk_table.num_entries) { in dcn316_clk_mgr_helper_populate_bw_params()
556 bw_params->wm_table.entries[i].valid = false; in dcn316_clk_mgr_helper_populate_bw_params()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
A Dvg_clk_mgr.c394 if (!bw_params->wm_table.entries[i].valid) in vg_build_watermark_ranges()
412 bw_params->clk_table.entries[i].dcfclk_mhz; in vg_build_watermark_ranges()
565 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; in vg_clk_mgr_helper_populate_bw_params() local
587 bw_params->clk_table.num_entries = j + 1; in vg_clk_mgr_helper_populate_bw_params()
600 bw_params->vram_type = bios_info->memory_type; in vg_clk_mgr_helper_populate_bw_params()
604 bw_params->wm_table.entries[i].wm_inst = i; in vg_clk_mgr_helper_populate_bw_params()
606 if (i >= bw_params->clk_table.num_entries) { in vg_clk_mgr_helper_populate_bw_params()
607 bw_params->wm_table.entries[i].valid = false; in vg_clk_mgr_helper_populate_bw_params()
612 bw_params->wm_table.entries[i].valid = true; in vg_clk_mgr_helper_populate_bw_params()
615 if (bw_params->vram_type == LpDdr4MemType) { in vg_clk_mgr_helper_populate_bw_params()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
A Drn_clk_mgr.c462 if (!bw_params->wm_table.entries[i].valid) in build_watermark_ranges()
664 bw_params->clk_table.num_entries = j + 1; in rn_clk_mgr_helper_populate_bw_params()
672 bw_params->clk_table.entries[i].voltage); in rn_clk_mgr_helper_populate_bw_params()
675 bw_params->vram_type = bios_info->memory_type; in rn_clk_mgr_helper_populate_bw_params()
679 bw_params->wm_table.entries[i].wm_inst = i; in rn_clk_mgr_helper_populate_bw_params()
681 if (i >= bw_params->clk_table.num_entries) { in rn_clk_mgr_helper_populate_bw_params()
682 bw_params->wm_table.entries[i].valid = false; in rn_clk_mgr_helper_populate_bw_params()
687 bw_params->wm_table.entries[i].valid = true; in rn_clk_mgr_helper_populate_bw_params()
690 if (bw_params->vram_type == LpDdr4MemType) { in rn_clk_mgr_helper_populate_bw_params()
769 clk_mgr->base.bw_params = &rn_bw_params; in rn_clk_mgr_construct()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
A Ddcn31_clk_mgr.c430 if (!bw_params->wm_table.entries[i].valid) in dcn31_build_watermark_ranges()
448 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn31_build_watermark_ranges()
561 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; in dcn31_clk_mgr_helper_populate_bw_params() local
584 bw_params->clk_table.num_entries = j + 1; in dcn31_clk_mgr_helper_populate_bw_params()
601 bw_params->clk_table.entries[i].wck_ratio = 2; in dcn31_clk_mgr_helper_populate_bw_params()
604 bw_params->clk_table.entries[i].wck_ratio = 4; in dcn31_clk_mgr_helper_populate_bw_params()
615 bw_params->vram_type = bios_info->memory_type; in dcn31_clk_mgr_helper_populate_bw_params()
621 bw_params->wm_table.entries[i].wm_inst = i; in dcn31_clk_mgr_helper_populate_bw_params()
623 if (i >= bw_params->clk_table.num_entries) { in dcn31_clk_mgr_helper_populate_bw_params()
624 bw_params->wm_table.entries[i].valid = false; in dcn31_clk_mgr_helper_populate_bw_params()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddcn31_fpu.c458 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn31_update_soc_for_wm_a()
469 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn315_update_soc_for_wm_a()
478 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us; in dcn315_update_soc_for_wm_a()
593 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn31_update_bw_bounding_box()
605 dcn3_1_soc.num_chans = bw_params->num_channels; in dcn31_update_bw_bounding_box()
670 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn315_update_bw_bounding_box()
678 if (bw_params->num_channels > 0) in dcn315_update_bw_bounding_box()
679 dcn3_15_soc.num_chans = bw_params->num_channels; in dcn315_update_bw_bounding_box()
680 if (bw_params->dram_channel_width_bytes > 0) in dcn315_update_bw_bounding_box()
732 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn316_update_bw_bounding_box()
[all …]
A Ddcn31_fpu.h47 void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
48 void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
49 void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
/drivers/gpu/drm/amd/display/dc/dml/dcn301/
A Ddcn301_fpu.c323 void dcn301_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn301_fpu_update_bw_bounding_box() argument
327 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn301_fpu_update_bw_bounding_box()
338 dcn3_01_soc.num_chans = bw_params->num_channels; in dcn301_fpu_update_bw_bounding_box()
421 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; in dcn301_fpu_calculate_wm_and_dlg() local
423 ASSERT(bw_params); in dcn301_fpu_calculate_wm_and_dlg()
426 vlevel_max = bw_params->clk_table.num_entries - 1; in dcn301_fpu_calculate_wm_and_dlg()
429 table_entry = &bw_params->wm_table.entries[WM_D]; in dcn301_fpu_calculate_wm_and_dlg()
437 table_entry = &bw_params->wm_table.entries[WM_C]; in dcn301_fpu_calculate_wm_and_dlg()
442 table_entry = &bw_params->wm_table.entries[WM_B]; in dcn301_fpu_calculate_wm_and_dlg()
448 table_entry = &bw_params->wm_table.entries[WM_A]; in dcn301_fpu_calculate_wm_and_dlg()
/drivers/media/tuners/
A Dtda18212.c36 static const u8 bw_params[][3] = { in tda18212_set_params() local
115 ret = regmap_write(dev->regmap, 0x23, bw_params[i][2]); in tda18212_set_params()
123 ret = regmap_write(dev->regmap, 0x0f, bw_params[i][0]); in tda18212_set_params()
128 buf[1] = bw_params[i][1]; in tda18212_set_params()
/drivers/gpu/drm/amd/display/dc/dml/dcn314/
A Ddcn314_fpu.c182 void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) in dcn314_update_bw_bounding_box_fpu() argument
184 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn314_update_bw_bounding_box_fpu()
198 if (bw_params->dram_channel_width_bytes > 0) in dcn314_update_bw_bounding_box_fpu()
199 dcn3_14_soc.dram_channel_width_bytes = bw_params->dram_channel_width_bytes; in dcn314_update_bw_bounding_box_fpu()
201 if (bw_params->num_channels > 0) in dcn314_update_bw_bounding_box_fpu()
202 dcn3_14_soc.num_chans = bw_params->num_channels; in dcn314_update_bw_bounding_box_fpu()
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddcn20_fpu.h81 void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
83 void dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params *bw_params);
A Ddcn20_fpu.c2246 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; in dcn21_calculate_wm() local
2248 ASSERT(bw_params); in dcn21_calculate_wm()
2291 vlevel_max = bw_params->clk_table.num_entries - 1; in dcn21_calculate_wm()
2295 table_entry = &bw_params->wm_table.entries[WM_D]; in dcn21_calculate_wm()
2303 table_entry = &bw_params->wm_table.entries[WM_C]; in dcn21_calculate_wm()
2308 table_entry = &bw_params->wm_table.entries[WM_B]; in dcn21_calculate_wm()
2314 table_entry = &bw_params->wm_table.entries[WM_A]; in dcn21_calculate_wm()
2406 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn21_update_bw_bounding_box()
2414 dcn2_1_soc.num_chans = bw_params->num_channels; in dcn21_update_bw_bounding_box()
2470 bw_params->wm_table.entries[WM_D].wm_inst = WM_D; in dcn21_clk_mgr_set_bw_params_wm_table()
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn30/
A Ddcn30_resource.c2098 void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn30_update_bw_bounding_box() argument
2123 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn30_update_bw_bounding_box()
2127 dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn30_update_bw_bounding_box()
2129 dcn30_bb_max_clk.max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn30_update_bw_bounding_box()
2131 dcn30_bb_max_clk.max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn30_update_bw_bounding_box()
2133 dcn30_bb_max_clk.max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn30_update_bw_bounding_box()
2156 num_uclk_states = bw_params->clk_table.num_entries; in dcn30_update_bw_bounding_box()
2164 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { in dcn30_update_bw_bounding_box()
2165 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; in dcn30_update_bw_bounding_box()
2174 bw_params->clk_table.entries[j].memclk_mhz * 16; in dcn30_update_bw_bounding_box()
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