Searched refs:c20 (Results 1 – 4 of 4) sorted by relevance
| /drivers/iio/pressure/ |
| A D | dps310.c | 89 s32 c00, c10, c20, c30, c01, c11, c21; member
116 u32 c00, c10, c20, c30, c01, c11, c21; in dps310_get_coefs() local
151 c20 = (coef[12] << 8) | coef[13]; in dps310_get_coefs()
152 data->c20 = sign_extend32(c20, 15); in dps310_get_coefs()
676 nums[2] = p * p * (s64)data->c20; in dps310_calculate_pressure()
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| /drivers/ata/pata_parport/ |
| A D | Kconfig | 128 tristate "OnSpec 90c20 protocol"
131 This option enables support for the (obsolete) 90c20 parallel port
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| /drivers/gpu/drm/i915/display/ |
| A D | intel_cx0_phy.c | 2241 struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20; in intel_c20_compute_hdmi_tmds_pll()
2355 crtc_state->dpll_hw_state.cx0pll.c20 = *tables[i]; in intel_c20pll_calc_state()
2523 intel_c20pll_dump_hw_state(display, &hw_state->c20); in intel_cx0pll_dump_hw_state()
3049 intel_c20_pll_program(display, encoder, &pll_state->c20, is_dp, port_clock); in __intel_cx0pll_enable()
3460 intel_c20pll_readout_hw_state(encoder, &pll_state->c20); in intel_cx0pll_readout_hw_state()
3512 return mtl_compare_hw_state_c20(&a->c20, in intel_cx0pll_compare_hw_state()
3513 &b->c20); in intel_cx0pll_compare_hw_state()
3522 return intel_c20pll_calc_port_clock(encoder, &pll_state->c20); in intel_cx0pll_calc_port_clock()
3531 const struct intel_c20pll_state *mpll_sw_state = &state->dpll_hw_state.cx0pll.c20; in intel_c20pll_state_verify()
3607 intel_c20pll_state_verify(new_crtc_state, crtc, encoder, &mpll_hw_state.c20); in intel_cx0pll_state_verify()
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| A D | intel_dpll_mgr.h | 263 struct intel_c20pll_state c20; member
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