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Searched refs:cache_line_size (Results 1 – 25 of 44) sorted by relevance

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/drivers/gpu/drm/amd/amdkfd/
A Dkfd_crat.c59 .cache_line_size = 64,
69 .cache_line_size = 64,
79 .cache_line_size = 64,
95 .cache_line_size = 64,
105 .cache_line_size = 64,
115 .cache_line_size = 64,
145 .cache_line_size = 64,
155 .cache_line_size = 64,
165 .cache_line_size = 64,
175 .cache_line_size = 64,
[all …]
A Dkfd_crat.h168 uint16_t cache_line_size; member
304 uint32_t cache_line_size; member
/drivers/net/ethernet/mellanox/mlx5/core/
A Dalloc.c136 u32 db_per_page = PAGE_SIZE / cache_line_size(); in mlx5_alloc_db_pgdir()
165 u32 db_per_page = PAGE_SIZE / cache_line_size(); in mlx5_alloc_db_from_pgdir()
177 offset = db->index * cache_line_size(); in mlx5_alloc_db_from_pgdir()
218 u32 db_per_page = PAGE_SIZE / cache_line_size(); in mlx5_db_free()
A Dwc.c120 if (MLX5_CAP_GEN(mdev, cqe_128_always) && cache_line_size() >= 128) in mlx5_wc_create_cq()
/drivers/s390/cio/
A Dairq.c141 if ((cache_line_size() * BITS_PER_BYTE) < bits in airq_iv_create()
308 cache_line_size(), in airq_init()
309 cache_line_size(), PAGE_SIZE); in airq_init()
/drivers/infiniband/sw/rxe/
A Drxe_queue.c77 if (elem_size < cache_line_size()) in rxe_queue_init()
78 elem_size = cache_line_size(); in rxe_queue_init()
/drivers/infiniband/hw/hfi1/
A Dmmu_rb.c51 free_ptr = kzalloc(sizeof(*h) + cache_line_size() - 1, GFP_KERNEL); in hfi1_mmu_rb_register()
55 h = PTR_ALIGN(free_ptr, cache_line_size()); in hfi1_mmu_rb_register()
/drivers/pci/endpoint/
A Dpci-ep-cfs.c437 PCI_EPF_HEADER_R(cache_line_size)
438 PCI_EPF_HEADER_W_u8(cache_line_size)
455 CONFIGFS_ATTR(pci_epf_, cache_line_size);
/drivers/staging/vc04_services/interface/vchiq_arm/
A Dvchiq_arm.h34 unsigned int cache_line_size; member
A Dvchiq_core.c1507 unsigned int cache_line_size; in create_pagelist() local
1660 cache_line_size = drv_mgmt->info->cache_line_size; in create_pagelist()
1662 ((pagelist->offset & (cache_line_size - 1)) || in create_pagelist()
1663 ((pagelist->offset + pagelist->length) & (cache_line_size - 1)))) { in create_pagelist()
1693 unsigned int cache_line_size; in free_pagelist() local
1708 cache_line_size = drv_mgmt->info->cache_line_size; in free_pagelist()
1715 head_bytes = (cache_line_size - pagelist->offset) & in free_pagelist()
1716 (cache_line_size - 1); in free_pagelist()
1718 (cache_line_size - 1); in free_pagelist()
1731 (PAGE_SIZE - 1) & ~(cache_line_size - 1), in free_pagelist()
[all …]
A Dvchiq_arm.c68 .cache_line_size = 32,
72 .cache_line_size = 64,
205 drv_mgmt->fragments_size = 2 * drv_mgmt->info->cache_line_size; in vchiq_platform_init()
/drivers/pci/
A Dpci-acpi.c148 u8 cache_line_size; /* Not applicable to PCIe */ member
156 .cache_line_size = 8,
175 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpx->cache_line_size); in program_hpx_type0()
210 hpx0->cache_line_size = fields[2].integer.value; in decode_type0_hpx_record()
754 hpx0.cache_line_size = fields[0].integer.value; in acpi_run_hpp()
A Dpci-bridge-emul.h14 u8 cache_line_size; member
A Dpci-bridge-emul.c356 bridge->conf.cache_line_size = 0x10; in pci_bridge_emul_init()
/drivers/edac/
A Di7core_edac.c1983 const int cache_line_size = 64; in set_sdram_scrub_rate() local
1991 cache_line_size * 1000000; in set_sdram_scrub_rate()
2023 const u32 cache_line_size = 64; in get_sdram_scrub_rate() local
2043 1000000 * cache_line_size; in get_sdram_scrub_rate()
A Dthunderx_edac.c334 unsigned int cline_size = cache_line_size(); in inject_ecc_fn()
405 unsigned int cline_size = cache_line_size(); in thunderx_lmc_inject_ecc_write()
/drivers/net/ethernet/mellanox/mlx5/core/lib/
A Daso.c133 if (MLX5_CAP_GEN(mdev, cqe_128_always) && cache_line_size() >= 128) in mlx5_aso_create_cq()
/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource.c2036 cache_lines_used = total_size_in_mall_bytes / dc->caps.cache_line_size + 2; in dcn32_calculate_mall_ways_from_bytes()
2038 total_cache_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size; in dcn32_calculate_mall_ways_from_bytes()
2207 dc->caps.cache_line_size = 64; in dcn32_resource_construct()
2535 dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size; in dcn32_resource_construct()
/drivers/pci/controller/
A Dpcie-rockchip-ep.c138 rockchip_pcie_write(rockchip, hdr->cache_line_size, in rockchip_pcie_ep_write_header()
/drivers/iommu/
A Diova.c733 cache_line_size()); in iova_domain_init_rcaches()
/drivers/pci/controller/cadence/
A Dpcie-cadence-ep.c60 hdr->cache_line_size); in cdns_pcie_ep_write_header()
/drivers/gpu/drm/amd/display/dc/resource/dcn321/
A Ddcn321_resource.c1715 dc->caps.cache_line_size = 64; in dcn321_resource_construct()
2034 dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size; in dcn321_resource_construct()
/drivers/net/ethernet/mellanox/mlx4/
A Dfw.c1904 ((ilog2(cache_line_size()) - 4) << 5) | (1 << 4); in mlx4_INIT_HCA()
1953 dev->caps.eqe_size = cache_line_size(); in mlx4_INIT_HCA()
1954 dev->caps.cqe_size = cache_line_size(); in mlx4_INIT_HCA()
A Dmain.c378 if (cache_line_size() == 128 || cache_line_size() == 256) { in mlx4_enable_cqe_eqe_stride()
387 if (cache_line_size() != 32 && cache_line_size() != 64) in mlx4_enable_cqe_eqe_stride()
/drivers/net/ethernet/marvell/mvpp2/
A Dmvpp2.h844 ETH_HLEN + ETH_FCS_LEN, cache_line_size())

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