Searched refs:cacheline_size (Results 1 – 9 of 9) sorted by relevance
| /drivers/gpu/drm/i915/display/ |
| A D | i9xx_wm.c | 27 u8 cacheline_size; member
367 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
375 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
383 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
391 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
399 .cacheline_size = I915_FIFO_LINE_SIZE,
407 .cacheline_size = I915_FIFO_LINE_SIZE,
415 .cacheline_size = I915_FIFO_LINE_SIZE,
423 .cacheline_size = I830_FIFO_LINE_SIZE,
431 .cacheline_size = I830_FIFO_LINE_SIZE,
[all …]
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| /drivers/gpu/drm/amd/amdkfd/ |
| A D | kfd_topology.h | 105 uint32_t cacheline_size; member
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| A D | kfd_topology.c | 342 cache->cacheline_size); in kfd_cache_show()
1639 pcache->cacheline_size = pcache_info[cache_type].cache_line_size; in fill_in_l1_pcache()
1723 pcache->cacheline_size = pcache_info[cache_type].cache_line_size; in fill_in_l2_l3_pcache()
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| A D | kfd_crat.c | 1197 props->cacheline_size = cache->cache_line_size; in kfd_parse_subtype_cache()
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| /drivers/scsi/ |
| A D | myrb.h | 297 unsigned short cacheline_size; /* Bytes 104-105 */ member
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| A D | myrs.h | 413 enum myrs_cacheline_size cacheline_size; /* Byte 7 */ member
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| A D | myrs.c | 1575 if (ldev_info->cacheline_size) { in myrs_mode_sense()
1577 put_unaligned_be16(1 << ldev_info->cacheline_size, in myrs_mode_sense()
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| /drivers/pci/ |
| A D | pci.c | 4369 u8 cacheline_size; in pci_set_cacheline_size() local
4376 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); in pci_set_cacheline_size()
4377 if (cacheline_size >= pci_cache_line_size && in pci_set_cacheline_size()
4378 (cacheline_size % pci_cache_line_size) == 0) in pci_set_cacheline_size()
4384 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); in pci_set_cacheline_size()
4385 if (cacheline_size == pci_cache_line_size) in pci_set_cacheline_size()
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| /drivers/net/ethernet/broadcom/ |
| A D | tg3.c | 17137 int cacheline_size; in tg3_calc_dma_bndry() local
17143 cacheline_size = 1024; in tg3_calc_dma_bndry()
17145 cacheline_size = (int) byte * 4; in tg3_calc_dma_bndry()
17185 switch (cacheline_size) { in tg3_calc_dma_bndry()
17210 switch (cacheline_size) { in tg3_calc_dma_bndry()
17227 switch (cacheline_size) { in tg3_calc_dma_bndry()
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