Searched refs:caches (Results 1 – 8 of 8) sorted by relevance
73 struct list_head caches; member132 list_for_each_entry(tcache, &target->caches, node) { in hmat_get_extended_linear_cache_size()233 INIT_LIST_HEAD(&target->caches); in alloc_target()575 list_add_tail(&tcache->node, &target->caches); in hmat_parse_cache()883 list_for_each_entry(tcache, &target->caches, node) in hmat_register_target_cache()1042 list_for_each_entry_safe(tcache, cnext, &target->caches, node) { in hmat_free_structures()
219 the content of CPU caches without notifying those caches to221 to invalidate caches when those events occur. If that invalidation
25 Upon request, the driver caches the firmware image until
17 frequencies or larger L3 caches on processors supporting AMD 3D V-Cache
406 unsigned long caches; in update_balloon_stats() local412 caches = global_node_page_state(NR_FILE_PAGES); in update_balloon_stats()420 pages_to_bytes(caches)); in update_balloon_stats()
88 driver which controls the scaling of L3 caches on Qualcomm SoCs.
362 Support for error detection and correction on the primary caches of
331 The writecache target caches writes on persistent memory or SSD.
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