| /drivers/clk/ |
| A D | clk-rp1.c | 463 calc_rate += BIT(23); in get_pll_core_divider()
464 calc_rate >>= 24; in get_pll_core_divider()
469 return calc_rate; in get_pll_core_divider()
528 calc_rate >>= 24; in rp1_pll_core_recalc_rate()
530 return calc_rate; in rp1_pll_core_recalc_rate()
779 u64 calc_rate; in rp1_clock_recalc_rate() local
794 calc_rate = div64_u64(calc_rate, div); in rp1_clock_recalc_rate()
796 return calc_rate; in rp1_clock_recalc_rate()
985 *calc_rate = 0; in rp1_clock_choose_div_and_prate()
999 *calc_rate = 0; in rp1_clock_choose_div_and_prate()
[all …]
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| /drivers/clk/renesas/ |
| A D | clk-div6.c | 106 unsigned long prate, calc_rate, diff, best_rate, best_prate; in cpg_div6_clock_determine_rate() local
128 calc_rate = prate / div; in cpg_div6_clock_determine_rate()
129 diff = calc_rate > req->rate ? calc_rate - req->rate in cpg_div6_clock_determine_rate()
130 : req->rate - calc_rate; in cpg_div6_clock_determine_rate()
132 best_rate = calc_rate; in cpg_div6_clock_determine_rate()
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| /drivers/clk/actions/ |
| A D | owl-factor.c | 48 u64 calc_rate; in _get_table_val() local
51 calc_rate = parent_rate * clkt->mul; in _get_table_val()
52 do_div(calc_rate, clkt->div); in _get_table_val()
54 if ((unsigned long)calc_rate <= rate) { in _get_table_val()
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| /drivers/clk/spear/ |
| A D | clk.c | 14 unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt, in clk_round_rate_index() argument
21 rate = calc_rate(hw, parent_rate, *index); in clk_round_rate_index()
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| A D | clk.h | 128 unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt,
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| /drivers/clk/at91/ |
| A D | clk-pll.c | 279 unsigned long calc_rate; in clk_pll_restore_context() local
288 calc_rate = (pll->pms.parent_rate / PLL_DIV(pllr)) * in clk_pll_restore_context()
293 if (pll->pms.rate != calc_rate || in clk_pll_restore_context()
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| /drivers/clk/qcom/ |
| A D | clk-rcg2.c | 182 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div) in calc_rate() function
215 return calc_rate(parent_rate, m, n, mode, hid_div); in __clk_rcg2_recalc_rate()
315 rate = calc_rate(parent_rate, conf->n, conf->m, conf->n, conf->pre_div); in __clk_rcg2_select_conf()
498 req->rate = calc_rate(parent_rate, f->m, f->n, f->n, f->pre_div); in clk_rcg2_determine_gp_rate()
968 req->rate = calc_rate(req->best_parent_rate, in clk_edp_pixel_determine_rate()
1007 req->rate = calc_rate(parent_rate, 0, 0, 0, div); in clk_byte_determine_rate()
1064 req->rate = calc_rate(parent_rate, 0, 0, 0, div); in clk_byte2_determine_rate()
1645 f->freq = calc_rate(prate, f->m, f->n, mode, f->pre_div); in clk_rcg2_dfs_populate_freq()
1727 return calc_rate(parent_rate, m, n, mode, pre_div); in clk_rcg2_dfs_recalc_rate()
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| A D | clk-rcg.c | 326 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 pre_div) in calc_rate() function
363 return calc_rate(parent_rate, m, n, mode, pre_div); in clk_rcg_recalc_rate()
396 return calc_rate(parent_rate, m, n, mode, pre_div); in clk_dyn_rcg_recalc_rate()
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| /drivers/clk/tegra/ |
| A D | clk-tegra210.c | 1685 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1731 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1770 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1800 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1860 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1916 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1940 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1982 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2022 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2060 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
[all …]
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| A D | clk-pll.c | 820 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) { in clk_pll_set_rate()
857 pll->params->calc_rate(hw, &cfg, rate, *prate)) in clk_pll_round_rate()
1904 if (!pll->params->calc_rate) { in _tegra_clk_register_pll()
1906 pll->params->calc_rate = _calc_dynamic_ramp_rate; in _tegra_clk_register_pll()
1908 pll->params->calc_rate = _calc_rate; in _tegra_clk_register_pll()
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| A D | clk.h | 341 int (*calc_rate)(struct clk_hw *hw, member
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