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Searched refs:caps (Results 1 – 25 of 1084) sorted by relevance

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/drivers/media/platform/qcom/venus/
A Dhfi_platform_v4.c7 static const struct hfi_plat_caps caps[] = { variable
12 .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 96, 4096, 1},
16 .caps[4] = {HFI_CAPABILITY_SCALE_X, 4096, 65536, 1},
17 .caps[5] = {HFI_CAPABILITY_SCALE_Y, 4096, 65536, 1},
19 .caps[7] = {HFI_CAPABILITY_FRAMERATE, 1, 480, 1},
21 .caps[9] = {HFI_CAPABILITY_MAX_WORKMODES, 1, 3, 1},
151 .caps[13] = {HFI_CAPABILITY_BFRAME, 0, 1, 1},
188 .caps[13] = {HFI_CAPABILITY_BFRAME, 0, 1, 1},
225 .caps[13] = {HFI_CAPABILITY_BFRAME, 0, 1, 1},
250 *entries = ARRAY_SIZE(caps); in get_capabilities()
[all …]
A Dhfi_platform_v6.c7 static const struct hfi_plat_caps caps[] = { variable
12 .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 128, 8192, 1},
16 .caps[3] = {HFI_CAPABILITY_BITRATE, 1, 220000000, 1},
17 .caps[4] = {HFI_CAPABILITY_SCALE_X, 65536, 65536, 1},
20 .caps[7] = {HFI_CAPABILITY_FRAMERATE, 1, 960, 1},
45 .caps[7] = {HFI_CAPABILITY_FRAMERATE, 1, 960, 1},
151 .caps[13] = {HFI_CAPABILITY_BFRAME, 0, 1, 1},
188 .caps[13] = {HFI_CAPABILITY_BFRAME, 0, 1, 1},
225 .caps[13] = {HFI_CAPABILITY_BFRAME, 0, 0, 1},
250 *entries = ARRAY_SIZE(caps); in get_capabilities()
[all …]
A Dhfi_parser.c19 struct hfi_plat_caps *caps = core->caps, *cap; in init_codecs() local
50 cap = &caps[i]; in for_each_codec()
82 for_each_codec(core->caps, ARRAY_SIZE(core->caps), in parse_alloc_mode()
115 for_each_codec(core->caps, ARRAY_SIZE(core->caps), codecs, domain, in parse_profile_level()
129 memcpy(&cap->caps[cap->num_caps], caps, num * sizeof(*caps)); in fill_caps()
146 for_each_codec(core->caps, ARRAY_SIZE(core->caps), codecs, domain, in parse_caps()
255 caps = inst->core->caps; in parser_fini()
259 cap = &caps[i]; in parser_fini()
294 memset(core->caps, 0, sizeof(*caps) * MAX_CODEC_NUM); in hfi_platform_parser()
295 memcpy(core->caps, caps, sizeof(*caps) * entries); in hfi_platform_parser()
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/drivers/gpu/drm/msm/disp/mdp5/
A Dmdp5_cfg.c21 .caps = MDP_CAP_SMP |
110 .caps = MDP_CAP_SMP |
191 .caps = MDP_CAP_SMP |
278 .caps = MDP_CAP_SMP |
379 .caps = MDP_CAP_SMP |
451 .caps = MDP_CAP_SMP |
530 .caps = MDP_CAP_SMP |
630 .caps = MDP_CAP_DSC |
840 .caps = MDP_CAP_CDM,
932 .caps = MDP_CAP_CDM,
[all …]
A Dmdp5_pipe.c10 uint32_t caps, uint32_t blkcfg, in mdp5_pipe_assign() argument
45 if (caps & ~cur->caps) in mdp5_pipe_assign()
52 if (cur->caps & MDP_PIPE_CAP_CURSOR && in mdp5_pipe_assign()
59 if (!(*hwpipe) || (hweight_long(cur->caps & ~caps) < in mdp5_pipe_assign()
60 hweight_long((*hwpipe)->caps & ~caps))) { in mdp5_pipe_assign()
70 if (r_cur->caps != cur->caps) in mdp5_pipe_assign()
110 (*hwpipe)->name, plane->name, caps); in mdp5_pipe_assign()
115 (*r_hwpipe)->name, plane->name, caps); in mdp5_pipe_assign()
156 uint32_t reg_offset, uint32_t caps) in mdp5_pipe_init() argument
167 hwpipe->caps = caps; in mdp5_pipe_init()
/drivers/net/wireless/ath/ath5k/
A Dcaps.c39 ee_header = caps->cap_eeprom.ee_header; in ath5k_hw_set_capabilities()
46 caps->cap_range.range_5ghz_min = 5120; in ath5k_hw_set_capabilities()
47 caps->cap_range.range_5ghz_max = 5430; in ath5k_hw_set_capabilities()
48 caps->cap_range.range_2ghz_min = 0; in ath5k_hw_set_capabilities()
49 caps->cap_range.range_2ghz_max = 0; in ath5k_hw_set_capabilities()
91 if (!caps->cap_needs_2GHz_ovr) { in ath5k_hw_set_capabilities()
94 caps->cap_mode); in ath5k_hw_set_capabilities()
99 caps->cap_mode); in ath5k_hw_set_capabilities()
115 caps->cap_has_phyerr_counters = true; in ath5k_hw_set_capabilities()
121 caps->cap_has_mrr_support = true; in ath5k_hw_set_capabilities()
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/drivers/net/ethernet/mellanox/mlx4/
A Dmain.c333 dev->caps.port_mask[i] = dev->caps.port_type[i]; in mlx4_set_port_mask()
601 dev->caps.port_type[i] = dev->caps.suggested_type[i] ? in mlx4_dev_cap()
630 dev->caps.possible_type[i] = dev->caps.port_type[i]; in mlx4_dev_cap()
865 struct mlx4_caps *caps = &dev->caps; in mlx4_slave_special_qp_cap() local
869 caps->spec_qps = kcalloc(caps->num_ports, sizeof(*caps->spec_qps), GFP_KERNEL); in mlx4_slave_special_qp_cap()
885 caps->port_mask[i] = caps->port_type[i]; in mlx4_slave_special_qp_cap()
1026 if (dev->caps.uar_page_size * (dev->caps.num_uars - in mlx4_slave_cap()
1031 dev->caps.uar_page_size * dev->caps.num_uars, in mlx4_slave_cap()
1809 dev->caps.num_mgms + dev->caps.num_amgms, in mlx4_init_icm()
1810 dev->caps.num_mgms + dev->caps.num_amgms, in mlx4_init_icm()
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/drivers/net/ethernet/netronome/nfp/
A Dnfp_net_ctrl.c14 memset(caps, 0, sizeof(*caps)); in nfp_net_tlv_caps_reset()
15 caps->me_freq_mhz = 1200; in nfp_net_tlv_caps_reset()
16 caps->mbox_off = NFP_NET_CFG_MBOX_BASE; in nfp_net_tlv_caps_reset()
37 caps->crypto_ops = readl(data); in nfp_net_tls_parse_crypto_ops()
45 struct nfp_net_tlv_caps *caps) in nfp_net_tlv_caps_parse() argument
51 nfp_net_tlv_caps_reset(caps); in nfp_net_tlv_caps_parse()
99 caps->me_freq_mhz = readl(data); in nfp_net_tlv_caps_parse()
103 caps->mbox_off = 0; in nfp_net_tlv_caps_parse()
104 caps->mbox_len = 0; in nfp_net_tlv_caps_parse()
107 caps->mbox_len = length; in nfp_net_tlv_caps_parse()
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/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/
A Ddr_domain.c9 ((dmn)->info.caps.dmn_type##_sw_owner || \
10 ((dmn)->info.caps.dmn_type##_sw_owner_v2 && \
281 struct mlx5dr_cmd_caps *caps = &dmn->info.caps; in dr_domain_add_vport_cap() local
310 struct mlx5dr_cmd_caps *caps = &dmn->info.caps; in dr_domain_is_esw_mgr_vport() local
319 struct mlx5dr_cmd_caps *caps = &dmn->info.caps; in mlx5dr_domain_get_vport_cap() local
326 return &caps->vports.uplink_caps; in mlx5dr_domain_get_vport_cap()
357 if (!dmn->info.caps.eswitch_manager) in dr_domain_query_fdb_caps()
364 dmn->info.caps.fdb_sw_owner = dmn->info.caps.esw_caps.sw_owner; in dr_domain_query_fdb_caps()
365 dmn->info.caps.fdb_sw_owner_v2 = dmn->info.caps.esw_caps.sw_owner_v2; in dr_domain_query_fdb_caps()
366 dmn->info.caps.esw_rx_drop_address = dmn->info.caps.esw_caps.drop_icm_address_rx; in dr_domain_query_fdb_caps()
[all …]
A Ddr_matcher.c232 struct mlx5dr_cmd_caps *caps = &dmn->info.caps; in dr_mask_is_tnl_gtpu_flex_parser_0() local
247 struct mlx5dr_cmd_caps *caps = &dmn->info.caps; in dr_mask_is_tnl_gtpu_flex_parser_1() local
529 &mask, &dmn->info.caps, in dr_matcher_set_ste_builders()
533 &mask, &dmn->info.caps, in dr_matcher_set_ste_builders()
538 &mask, &dmn->info.caps, in dr_matcher_set_ste_builders()
543 &mask, &dmn->info.caps, in dr_matcher_set_ste_builders()
564 &mask, &dmn->info.caps, in dr_matcher_set_ste_builders()
568 &mask, &dmn->info.caps, in dr_matcher_set_ste_builders()
573 &mask, &dmn->info.caps, in dr_matcher_set_ste_builders()
639 &mask, &dmn->info.caps, in dr_matcher_set_ste_builders()
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A Ddr_cmd.c71 caps->drop_icm_address_rx = in mlx5dr_cmd_query_esw_caps()
74 caps->drop_icm_address_tx = in mlx5dr_cmd_query_esw_caps()
77 caps->uplink_icm_address_rx = in mlx5dr_cmd_query_esw_caps()
80 caps->uplink_icm_address_tx = in mlx5dr_cmd_query_esw_caps()
84 if (!caps->sw_owner_v2) in mlx5dr_cmd_query_esw_caps()
197 caps->nic_rx_drop_address = in mlx5dr_cmd_query_device()
199 caps->nic_tx_drop_address = in mlx5dr_cmd_query_device()
201 caps->nic_tx_allow_address = in mlx5dr_cmd_query_device()
207 if (!caps->rx_sw_owner_v2) in mlx5dr_cmd_query_device()
209 if (!caps->tx_sw_owner_v2) in mlx5dr_cmd_query_device()
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/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_dwb.c47 if (caps) { in dwb1_get_caps()
48 caps->adapter_id = 0; /* we only support 1 adapter currently */ in dwb1_get_caps()
49 caps->hw_version = DCN_VERSION_1_0; in dwb1_get_caps()
50 caps->num_pipes = 2; in dwb1_get_caps()
51 memset(&caps->reserved, 0, sizeof(caps->reserved)); in dwb1_get_caps()
52 memset(&caps->reserved2, 0, sizeof(caps->reserved2)); in dwb1_get_caps()
53 caps->sw_version = dwb_ver_1_0; in dwb1_get_caps()
54 caps->caps.support_dwb = true; in dwb1_get_caps()
55 caps->caps.support_ogam = false; in dwb1_get_caps()
56 caps->caps.support_wbscl = true; in dwb1_get_caps()
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/drivers/infiniband/hw/hns/
A Dhns_roce_main.c70 if (port >= hr_dev->caps.num_ports) in hns_roce_add_gid()
84 if (port >= hr_dev->caps.num_ports) in hns_roce_del_gid()
791 hr_dev->caps.num_mtpts); in hns_roce_init_hem()
799 hr_dev->caps.num_qps); in hns_roce_init_hem()
809 hr_dev->caps.num_qps); in hns_roce_init_hem()
821 hr_dev->caps.num_qps); in hns_roce_init_hem()
831 hr_dev->caps.num_cqs); in hns_roce_init_hem()
853 hr_dev->caps.sccc_sz, in hns_roce_init_hem()
854 hr_dev->caps.num_qps); in hns_roce_init_hem()
886 if (hr_dev->caps.gmv_entry_sz) { in hns_roce_init_hem()
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/drivers/gpu/drm/stm/
A Dltdc.c1373 if (ldev->caps.ycbcr_input) { in ltdc_plane_atomic_update()
1595 if (ldev->caps.ycbcr_input) { in ltdc_plane_create()
1620 if (ldev->caps.ycbcr_input) { in ltdc_plane_create()
1664 if (ldev->caps.crc) in ltdc_crtc_init()
1817 ldev->caps.nb_irq = 2; in ltdc_get_caps()
1821 ldev->caps.crc = false; in ltdc_get_caps()
1835 ldev->caps.nb_irq = 4; in ltdc_get_caps()
1839 ldev->caps.crc = false; in ltdc_get_caps()
1853 ldev->caps.nb_irq = 2; in ltdc_get_caps()
1857 ldev->caps.crc = true; in ltdc_get_caps()
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/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/
A Dcontext.c91 struct mlx5hws_cmd_query_caps *caps = ctx->caps; in hws_context_check_hws_supp() local
94 if (!caps->wqe_based_update) { in hws_context_check_hws_supp()
99 if (!caps->eswitch_manager) { in hws_context_check_hws_supp()
105 if ((!caps->nic_ft.reparse || in hws_context_check_hws_supp()
106 (!caps->fdb_ft.reparse && caps->eswitch_manager)) || in hws_context_check_hws_supp()
113 if (!IS_BIT_SET(caps->ste_format, MLX5_IFC_RTC_STE_FORMAT_8DW)) { in hws_context_check_hws_supp()
204 ctx->caps = kzalloc(sizeof(*ctx->caps), GFP_KERNEL); in mlx5hws_context_open()
205 if (!ctx->caps) in mlx5hws_context_open()
208 ret = mlx5hws_cmd_query_caps(mdev, ctx->caps); in mlx5hws_context_open()
227 kfree(ctx->caps); in mlx5hws_context_open()
[all …]
A Ddebug.c272 struct mlx5hws_cmd_query_caps *caps = ctx->caps; in hws_debug_dump_context_caps() local
277 caps->fw_ver, in hws_debug_dump_context_caps()
278 caps->wqe_based_update, in hws_debug_dump_context_caps()
279 caps->ste_format, in hws_debug_dump_context_caps()
284 caps->flex_protocols, in hws_debug_dump_context_caps()
285 caps->rtc_reparse_mode, in hws_debug_dump_context_caps()
286 caps->rtc_index_mode, in hws_debug_dump_context_caps()
295 caps->nic_ft.max_level, in hws_debug_dump_context_caps()
296 caps->nic_ft.reparse, in hws_debug_dump_context_caps()
298 caps->fdb_ft.reparse, in hws_debug_dump_context_caps()
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/drivers/gpu/drm/amd/display/dc/dwb/dcn30/
A Ddcn30_dwb.c48 if (caps) { in dwb3_get_caps()
50 caps->hw_version = DCN_VERSION_3_0; in dwb3_get_caps()
51 caps->num_pipes = 2; in dwb3_get_caps()
52 memset(&caps->reserved, 0, sizeof(caps->reserved)); in dwb3_get_caps()
53 memset(&caps->reserved2, 0, sizeof(caps->reserved2)); in dwb3_get_caps()
54 caps->sw_version = dwb_ver_2_0; in dwb3_get_caps()
55 caps->caps.support_dwb = true; in dwb3_get_caps()
56 caps->caps.support_ogam = true; in dwb3_get_caps()
57 caps->caps.support_wbscl = true; in dwb3_get_caps()
58 caps->caps.support_ocsc = false; in dwb3_get_caps()
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/drivers/infiniband/hw/vmw_pvrdma/
A Dpvrdma_verbs.c74 props->fw_ver = dev->dsr->caps.fw_ver; in pvrdma_query_device()
80 props->hw_ver = dev->dsr->caps.hw_ver; in pvrdma_query_device()
81 props->max_qp = dev->dsr->caps.max_qp; in pvrdma_query_device()
87 dev->dsr->caps.max_sge_rd); in pvrdma_query_device()
88 props->max_srq = dev->dsr->caps.max_srq; in pvrdma_query_device()
91 props->max_cq = dev->dsr->caps.max_cq; in pvrdma_query_device()
92 props->max_cqe = dev->dsr->caps.max_cqe; in pvrdma_query_device()
93 props->max_mr = dev->dsr->caps.max_mr; in pvrdma_query_device()
94 props->max_pd = dev->dsr->caps.max_pd; in pvrdma_query_device()
98 dev->dsr->caps.atomic_ops & in pvrdma_query_device()
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/drivers/crypto/stm32/
A Dstm32-cryp.c403 if (cryp->caps->iv_protection) in stm32_cryp_get_iv()
414 if (cryp->caps->iv_protection) in stm32_cryp_get_iv()
525 r_id = c->caps->k1l; in stm32_cryp_hw_write_key()
532 r_id = c->caps->k3r; in stm32_cryp_hw_write_key()
716 if (!cryp->caps->padding_wa) in stm32_cryp_ccm_init()
779 if (cryp->caps->kp_mode) in stm32_cryp_hw_init()
1831 if (cryp->caps->swap_final) in stm32_cryp_read_auth_tag()
1840 if (cryp->caps->swap_final) in stm32_cryp_read_auth_tag()
1857 if (!cryp->caps->padding_wa) in stm32_cryp_read_auth_tag()
2126 if (cryp->caps->padding_wa) { in stm32_cryp_irq_write_data()
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/drivers/gpu/drm/omapdrm/
A Domap_overlay.c28 u32 caps, u32 fourcc) in omap_plane_find_free_overlay() argument
33 DBG("caps: %x fourcc: %x", caps, fourcc); in omap_plane_find_free_overlay()
39 cur->idx, cur->id, cur->caps); in omap_plane_find_free_overlay()
46 if (caps & ~cur->caps) in omap_plane_find_free_overlay()
69 u32 caps, u32 fourcc, struct omap_hw_overlay **overlay, in omap_overlay_assign() argument
86 caps, fourcc); in omap_overlay_assign()
101 r_ovl->name, plane->name, caps); in omap_overlay_assign()
157 enum omap_overlay_caps caps) in omap_overlay_init() argument
167 overlay->caps = caps; in omap_overlay_init()
179 enum omap_overlay_caps caps; in omap_hwoverlays_init() local
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/drivers/pmdomain/mediatek/
A Dmt8188-pm-domains.h78 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
88 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
98 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
120 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
128 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
136 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
280 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
385 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
402 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
450 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
[all …]
A Dmt8195-pm-domains.h66 .caps = MTK_SCPD_ACTIVE_WAKEUP,
82 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
92 .caps = MTK_SCPD_ACTIVE_WAKEUP,
187 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
197 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
207 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
217 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
227 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
358 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
375 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
[all …]
A Dmt8186-pm-domains.h68 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
78 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
88 .caps = MTK_SCPD_ACTIVE_WAKEUP,
98 .caps = MTK_SCPD_ACTIVE_WAKEUP,
141 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
151 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
173 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
195 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
205 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
215 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
[all …]
/drivers/gpu/drm/arm/display/komeda/
A Dkomeda_format_caps.c16 const struct komeda_format_caps *caps; in komeda_get_format_caps() local
22 caps = &table->format_caps[id]; in komeda_get_format_caps()
24 if (fourcc != caps->fourcc) in komeda_get_format_caps()
28 return caps; in komeda_get_format_caps()
30 if (has_bits(afbc_features, caps->supported_afbc_features) && in komeda_get_format_caps()
31 has_bit(afbc_layout, caps->supported_afbc_layouts)) in komeda_get_format_caps()
32 return caps; in komeda_get_format_caps()
99 const struct komeda_format_caps *caps; in komeda_format_mod_supported() local
101 caps = komeda_get_format_caps(table, fourcc, modifier); in komeda_format_mod_supported()
102 if (!caps) in komeda_format_mod_supported()
[all …]
/drivers/mtd/nand/
A Decc-mtk.c60 const struct mtk_ecc_caps *caps; member
183 if (i == ecc->caps->num_ecc_strength) { in mtk_ecc_config()
206 config->strength * ecc->caps->parity_bits; in mtk_ecc_config()
232 err = err >> ((i % 4) * ecc->caps->err_shift); in mtk_ecc_get_stats()
233 err &= ecc->caps->err_mask; in mtk_ecc_get_stats()
234 if (err == ecc->caps->err_mask) { in mtk_ecc_get_stats()
335 ecc->caps->ecc_regs[ECC_ENCIRQ_EN]); in mtk_ecc_enable()
338 ecc->caps->ecc_regs[ECC_DECIRQ_EN]); in mtk_ecc_enable()
422 ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00], in mtk_ecc_encode()
457 return ecc->caps->parity_bits; in mtk_ecc_get_parity_bits()
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