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/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_kms.c673 yuv_supported = !!dpu_kms->catalog->cdm; in _dpu_kms_initialize_displayport()
783 if (dpu_kms->catalog->wb_count) { in _dpu_kms_setup_displays()
811 const struct dpu_mdss_cfg *catalog; in _dpu_kms_drm_obj_init() local
817 catalog = dpu_kms->catalog; in _dpu_kms_drm_obj_init()
830 if (catalog->cwb_count > 0) in _dpu_kms_drm_obj_init()
849 type, catalog->sspp[i].features, in _dpu_kms_drm_obj_init()
902 dpu_kms->catalog = NULL; in _dpu_kms_hw_destroy()
950 cat = dpu_kms->catalog; in dpu_kms_mdp_snapshot()
1176 if (!dpu_kms->catalog) { in dpu_kms_hw_init()
1212 dpu_kms->catalog->mdp, in dpu_kms_hw_init()
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A Ddpu_encoder_phys_wb.c140 const struct dpu_mdss_cfg *catalog; in dpu_encoder_phys_wb_set_qos() local
143 if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) { in dpu_encoder_phys_wb_set_qos()
148 catalog = phys_enc->dpu_kms->catalog; in dpu_encoder_phys_wb_set_qos()
155 catalog->perf->danger_lut_tbl[DPU_QOS_LUT_USAGE_NRT]; in dpu_encoder_phys_wb_set_qos()
157 qos_cfg.safe_lut = catalog->perf->safe_lut_tbl[DPU_QOS_LUT_USAGE_NRT]; in dpu_encoder_phys_wb_set_qos()
159 qos_lut_tb = &catalog->perf->qos_lut_tbl[DPU_QOS_LUT_USAGE_NRT]; in dpu_encoder_phys_wb_set_qos()
179 if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) { in dpu_encoder_phys_wb_setup_fb()
204 const struct dpu_perf_cfg *perf = phys_enc->dpu_kms->catalog->perf; in dpu_encoder_phys_wb_setup_fb()
231 if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5 && in dpu_encoder_phys_wb_setup_ctl()
556 if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5) in dpu_encoder_phys_wb_disable()
A Ddpu_plane.c88 const struct dpu_mdss_cfg *catalog; member
136 hw_latency_lines = catalog->perf->min_prefill_lines; in _dpu_plane_calc_bw()
214 fixed_buff_size = pdpu->catalog->caps->pixel_ram_size; in _dpu_plane_calc_fill_level()
275 cfg.safe_lut = pdpu->catalog->perf->safe_lut_tbl[lut_usage]; in _dpu_plane_set_qos_lut()
875 max_linewidth = pdpu->catalog->caps->max_linewidth; in dpu_plane_atomic_check_nosspp()
1219 dpu_kms->catalog->caps->max_linewidth)) { in dpu_plane_virtual_assign_resources()
1240 dpu_kms->catalog->caps->max_linewidth)) { in dpu_plane_virtual_assign_resources()
1414 const struct dpu_perf_cfg *perf = pdpu->catalog->perf; in dpu_plane_sspp_update_pipe()
1736 pdpu->catalog = kms->catalog; in dpu_plane_init_common()
1826 for (i = 0; i < kms->catalog->sspp_count; i++) { in dpu_plane_init_virtual()
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A Ddpu_crtc.c771 if (!dpu_kms->catalog->caps->has_3d_merge && in _dpu_crtc_check_and_setup_lm_bounds()
772 adj_mode->hdisplay > dpu_kms->catalog->caps->max_mixer_width) in _dpu_crtc_check_and_setup_lm_bounds()
784 if (drm_rect_width(r) > dpu_kms->catalog->caps->max_mixer_width) in _dpu_crtc_check_and_setup_lm_bounds()
1358 else if (dpu_kms->catalog->caps->has_3d_merge) in dpu_crtc_get_topology()
1541 if (!dpu_kms->catalog->caps->has_3d_merge && in dpu_crtc_mode_valid()
1542 mode->hdisplay > dpu_kms->catalog->caps->max_mixer_width) in dpu_crtc_mode_valid()
1548 2 * dpu_kms->catalog->caps->max_mixer_width, in dpu_crtc_mode_valid()
1823 if (dpu_kms->catalog->dspp_count) in dpu_crtc_init()
A Ddpu_vbif.c303 for (i = 0; i < dpu_kms->catalog->vbif_count; i++) { in dpu_debugfs_vbif_init()
304 const struct dpu_vbif_cfg *vbif = &dpu_kms->catalog->vbif[i]; in dpu_debugfs_vbif_init()
A Ddpu_kms.h62 const struct dpu_mdss_cfg *catalog; member
A Ddpu_writeback.c24 return drm_add_modes_noedid(connector, dpu_kms->catalog->caps->max_mixer_width, in dpu_wb_conn_get_modes()
A Ddpu_encoder.c688 if (topology->num_intf >= 2 || dpu_kms->catalog->dsc_count >= 2) in dpu_encoder_update_topology()
1430 static struct dpu_hw_intf *dpu_encoder_get_intf(const struct dpu_mdss_cfg *catalog, in dpu_encoder_get_intf() argument
1439 for (i = 0; i < catalog->intf_count; i++) { in dpu_encoder_get_intf()
1440 if (catalog->intf[i].type == type in dpu_encoder_get_intf()
1441 && catalog->intf[i].controller_id == controller_id) { in dpu_encoder_get_intf()
1442 return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id); in dpu_encoder_get_intf()
2648 dpu_kms->catalog->caps->has_idle_pc; in dpu_encoder_setup_display()
2671 phys_params.hw_intf = dpu_encoder_get_intf(dpu_kms->catalog, &dpu_kms->rm, in dpu_encoder_setup_display()
A Ddpu_encoder_phys_cmd.c72 if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5 && in _dpu_encoder_phys_cmd_update_intf_cfg()
763 if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5) in dpu_encoder_phys_cmd_init()
A Ddpu_encoder_phys_vid.c380 return !(phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5) && in dpu_encoder_phys_vid_needs_single_flush()

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