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Searched refs:ccm_base (Results 1 – 9 of 9) sorted by relevance

/drivers/clk/imx/
A Dclk-imx8mp.c553 void __iomem *anatop_base, *ccm_base; in imx8mp_clocks_probe() local
564 ccm_base = devm_platform_ioremap_resource(pdev, 0); in imx8mp_clocks_probe()
565 if (WARN_ON(IS_ERR(ccm_base))) in imx8mp_clocks_probe()
566 return PTR_ERR(ccm_base); in imx8mp_clocks_probe()
700 hws[IMX8MP_CLK_CAN1] = imx8m_clk_hw_composite("can1", imx8mp_can1_sels, ccm_base + 0xa200); in imx8mp_clocks_probe()
701 hws[IMX8MP_CLK_CAN2] = imx8m_clk_hw_composite("can2", imx8mp_can2_sels, ccm_base + 0xa280); in imx8mp_clocks_probe()
703 hws[IMX8MP_CLK_I2C5] = imx8m_clk_hw_composite("i2c5", imx8mp_i2c5_sels, ccm_base + 0xa480); in imx8mp_clocks_probe()
704 hws[IMX8MP_CLK_I2C6] = imx8m_clk_hw_composite("i2c6", imx8mp_i2c6_sels, ccm_base + 0xa500); in imx8mp_clocks_probe()
705 hws[IMX8MP_CLK_SAI1] = imx8m_clk_hw_composite("sai1", imx8mp_sai1_sels, ccm_base + 0xa580); in imx8mp_clocks_probe()
706 hws[IMX8MP_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mp_sai2_sels, ccm_base + 0xa600); in imx8mp_clocks_probe()
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A Dclk-imxrt1050.c38 void __iomem *ccm_base; in imxrt1050_clocks_probe() local
108 ccm_base = devm_platform_ioremap_resource(pdev, 0); in imxrt1050_clocks_probe()
109 if (WARN_ON(IS_ERR(ccm_base))) { in imxrt1050_clocks_probe()
110 ret = PTR_ERR(ccm_base); in imxrt1050_clocks_probe()
117 hws[IMXRT1050_CLK_PERIPH_SEL] = imx_clk_hw_mux("periph_sel", ccm_base + 0x14, 25, 1, in imxrt1050_clocks_probe()
119 hws[IMXRT1050_CLK_USDHC1_SEL] = imx_clk_hw_mux("usdhc1_sel", ccm_base + 0x1c, 16, 1, in imxrt1050_clocks_probe()
123 hws[IMXRT1050_CLK_LPUART_SEL] = imx_clk_hw_mux("lpuart_sel", ccm_base + 0x24, 6, 1, in imxrt1050_clocks_probe()
125 hws[IMXRT1050_CLK_LCDIF_SEL] = imx_clk_hw_mux("lcdif_sel", ccm_base + 0x38, 15, 3, in imxrt1050_clocks_probe()
127 hws[IMXRT1050_CLK_PER_CLK_SEL] = imx_clk_hw_mux("per_sel", ccm_base + 0x1C, 6, 1, in imxrt1050_clocks_probe()
149 hws[IMXRT1050_CLK_DMA] = imx_clk_hw_gate("dma", "ipg", ccm_base + 0x7C, 6); in imxrt1050_clocks_probe()
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A Dclk-vf610.c14 #define CCM_CCR (ccm_base + 0x00)
15 #define CCM_CSR (ccm_base + 0x04)
16 #define CCM_CCSR (ccm_base + 0x08)
17 #define CCM_CACRR (ccm_base + 0x0c)
18 #define CCM_CSCMR1 (ccm_base + 0x10)
25 #define CCM_CISR (ccm_base + 0x30)
26 #define CCM_CIMR (ccm_base + 0x34)
27 #define CCM_CGPR (ccm_base + 0x3c)
69 static void __iomem *ccm_base; variable
205 ccm_base = of_iomap(np, 0); in vf610_clocks_init()
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A Dclk-imx5.c30 #define MXC_CCM_CCR (ccm_base + 0x00)
32 #define MXC_CCM_CSR (ccm_base + 0x08)
282 void __iomem *ccm_base; in mx50_clocks_init() local
298 ccm_base = of_iomap(np, 0); in mx50_clocks_init()
299 WARN_ON(!ccm_base); in mx50_clocks_init()
367 void __iomem *ccm_base; in mx51_clocks_init() local
383 ccm_base = of_iomap(np, 0); in mx51_clocks_init()
384 WARN_ON(!ccm_base); in mx51_clocks_init()
473 void __iomem *ccm_base; in mx53_clocks_init() local
493 ccm_base = of_iomap(np, 0); in mx53_clocks_init()
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A Dclk.c32 void imx_mmdc_mask_handshake(void __iomem *ccm_base, in imx_mmdc_mask_handshake() argument
37 reg = readl_relaxed(ccm_base + CCM_CCDR); in imx_mmdc_mask_handshake()
39 writel_relaxed(reg, ccm_base + CCM_CCDR); in imx_mmdc_mask_handshake()
A Dclk-imx6sl.c102 static void __iomem *ccm_base; variable
129 if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) { in imx6sl_get_arm_divider_for_wait()
170 saved_arm_div = readl_relaxed(ccm_base + CACRR); in imx6sl_set_wait_clk()
171 writel_relaxed(arm_div_for_wait, ccm_base + CACRR); in imx6sl_set_wait_clk()
173 writel_relaxed(saved_arm_div, ccm_base + CACRR); in imx6sl_set_wait_clk()
175 while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY) in imx6sl_set_wait_clk()
291 ccm_base = base; in imx6sl_clocks_init()
A Dclk-imx6q.c271 static void mmdc_ch1_disable(void __iomem *ccm_base) in mmdc_ch1_disable() argument
279 reg = readl_relaxed(ccm_base + CCM_CCSR); in mmdc_ch1_disable()
281 writel_relaxed(reg, ccm_base + CCM_CCSR); in mmdc_ch1_disable()
284 static void mmdc_ch1_reenable(void __iomem *ccm_base) in mmdc_ch1_reenable() argument
289 reg = readl_relaxed(ccm_base + CCM_CCSR); in mmdc_ch1_reenable()
291 writel_relaxed(reg, ccm_base + CCM_CCSR); in mmdc_ch1_reenable()
329 reg = readl_relaxed(ccm_base + CCM_CS2CDR); in init_ldb_clks()
371 mmdc_ch1_disable(ccm_base); in init_ldb_clks()
374 reg = readl_relaxed(ccm_base + CCM_CS2CDR); in init_ldb_clks()
379 writel_relaxed(reg, ccm_base + CCM_CS2CDR); in init_ldb_clks()
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A Dclk-imx25.c42 #define ccm(x) (ccm_base + (x))
77 static void __init __mx25_clocks_init(void __iomem *ccm_base) in __mx25_clocks_init() argument
79 BUG_ON(!ccm_base); in __mx25_clocks_init()
A Dclk.h21 void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn);

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